LP3972 datasheet(38/59 Pages) NSC

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2C Compatible Interface (Continued)

SYSTEM CONTROL REGISTER 2 (SCR2)

System Control Register 2 (SCR2) 8h’81

Bit

5**

3210

Designation

BBCS

SHBU

BPTR

WUP3

GPIO2

GPIO1

Reset Value

0010

Note: ** denotes one time factory programmable EPROM registers for default values

System Control Register 2 (SCR2) 8h’81 Definitions

Bit

Access

Name

Description

R/W

BBCS

Sets GPIO1 as control input for Back Up battery charger

0 - Back Up battery Charger GPIO Disabled

1 - Back Up battery Charger GPIO Pin Enabled

R/W

SHBU

Shut down Back up battery to prevent battery drain during

shipping

0 = Back up Battery Enabled

1 = Back up battery Disabled

R/W

BPTR

Bypass RTC_LDO Output Voltage to LDO 3 Output Voltage

Tracking

0 - RTC-LDO 3 Tracking enabled

1 - RTC-LDO 3 Tracking disabled, Default

R/W

WUP3

Spare Wakeup control input

0 - Active High

1 - Active Low

3:2

R/W

GPIO2

Configure direction and output sense of GPIO2 Pin

Data Code

2h’00

2h’01

2h’02

2h’03

GPIO2

Hi-Z

Output Low

Input

Output high

1:0

R/W

GPIO1

Configure direction and output sense of GPIO1 Pin

Data Code

2h’00

2h’01

2h’02

2h’03

GPIO1

Hi-Z

Output Low

Input

Output high

LP3972 Arkusz danych(PDF) 38 Page - National Semiconductor (TI)

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