MPC8560CPXAPDB datasheet(102/108 Pages) FREESCALE

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MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1

102

Freescale Semiconductor

Document Revision History

18 Document Revision History

Table 48 provides a revision history for this hardware specification.

Table 61. Document Revision History

Rev. No.

Substantive Change(s)

Original Customer Version.

1.1

Made updates throughout document.

Secrion 1.6.1—Added symbols and note for the GTX_CLK125 timing parameters.

Section 1.11.3—Updated pin list table: LGPL5/LSDAMUX to LGPL5, LA[27:29] and LA[30:31] to

LA[27:31], TRST to TRST, added GBE Clocking section and EC_GTX_CLK125 signal.

Figure 50—Updated pin 2 connection information.

1.2

Section 1.1.1—Updated feature list.

Section 1.2.1.1—Updated notes for Table 1.

Section 1.2.1.2—Removed 5-V PCI interface overshoot and undershoot figure.

Section 1.2.1.3—Added this section to summarize impedance driver settings for various interfaces.

Section 1.4—Updated rows in Reset Initialization timing specifications table. Added a table with DLL

and PLL timing specifications.

Section 1.5.2.2—Updated note 6 of DDR SDRAM Output AC Timing Specifications table.

Section 1.7—Changed the minimum input low current from -600 to -15

µA for the RGMII DC electrical

characteristics.

Section 1.7.2—Changed LCS[3:4] to TSEC1_TXD[6:5] in . Updated notes regarding LCS[3:4].

Section 1.13.2—Updated the mechanical dimensions diagram for the package.

Section 1.13.3—Updated the notes for LBCTL, TRIG_OUT, and ASLEEP.

Corrected pin assignments

for IIC_SDA and IIC_SCL. Corrected reserved pin assignment of V11 to U11. V11 is actually

PCI_STOP.

Section 1.14.1—Updated the table for frequency options with respect to platform/CCB frequencies.

Section 1.14.4—Edited Frequency options with respect to memory bus speeds.

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