TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

12

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

definitions of specifications and terminology

integral nonlinearity (INL)

Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.

The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level

1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to

the true straight line between these two points. This parameter is sometimes referred to as linearity error.

differential nonlinearity (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.

A differential nonlinearity error of less than

"1 LSB ensures no missing codes. This parameter is sometimes

referred to as differential error.

offset error

The first transition should occur at a level 1/2 LSB above zero. Offset is defined as the deviation of the actual

first code transition from that point.

gain error

The first code transition should occur for an analog value 1/2 LSB above nominal negative full scale (the voltage

applied to the REFBF terminal). The last transition should occur for an analog value 1 1/2 LSB below nominal

positive full scale (the voltage applied to the REFTF terminal). Gain error is the deviation of the actual difference

between the first and last code transitions from the ideal difference between the first and last code transitions.

pipeline delay (latency)

The number of clock cycles between conversion initiation on an input sample and the corresponding output data

being made available. Once the data pipeline is full, new valid output data are provided every clock cycle.

reference top/bottom offset

Resistance between the reference input and comparator input tap points causes offset errors. These errors can

be nulled out by using the force-sense connection as shown in the

driving the reference terminals section.

driving the analog input

Figure 12 shows an equivalent input circuit of the TLC876 sample-and-hold amplifier and it represents an

excellent first order approximation.

or discharge this capacitance to 10-bit accuracy in the sample period of one half of a clock cycle. When the

quickly settle (within 1/2 CLK period), and, therefore, the source is driving a low input impedance. However,

to maintain the charge and the equivalent input impedance is extremely high.

Adding series resistance between the output of the source and the AIN terminal reduces the drive requirements

placed on the source, as shown in Figure 13. To maintain the frequency performance outlined in the

specifications, the resistor should be limited to 200

Ω minus the source resistance or less. The maximum source