TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

13

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

driving the analog input (continued)

R

S v

1

2f

(CLK)

(C

E

ln 2048)

–R

SW

(1)

200

Ω limit on the total source resistance. For applications with an input clock less than 20 MHz, the size of the

series resistor can increase proportionally. Alternatively, adding a shunt capacitor between the AIN terminal and

analog ground can lower the ac source impedance. This capacitance value depends on the source resistance

and the required signal bandwidth.

The input span is determined by the reference voltages (see driving the reference terminals section).

Figure 12. TLC876 Simplified Equivalent Input

RS

AIN

VS

S1

RSW

Driving

Source

TLC876

CE

RS ≤ 200 Ω

AIN

VS

Figure 13. Sample TLC876 Drive Requirements

TLC876

Ideal Source

For many applications, particularly in single supply operation, ac-coupling offers a convenient way of biasing

the analog input signal at the proper signal range. Figure 14 shows a typical configuration for ac-coupling the

analog input signal to the TLC876. Maintaining the outlined specifications requires careful selection of the

f*3dB +

1

2

p

(R2) Ceq

(2)

where Ceq is the parallel combination of C1 and C2. Since C1 is typically a large electrolytic or tantalum

capacitor, the impedance becomes inductive at high frequencies. Adding a small ceramic or polystyrene

capacitor, C2 of approximately 0.01

µF, which is not inductive within the frequency range of interest, maintains

a low impedance. If the minimum expected input signal frequency is 20 kHz, and R2 equals 1 k

Ω and R1 equals

50

Ω, the parallel capacitance of C1 and C2 must be a minimum of 0.008 µF to avoid attenuating signals close

to 20 kHz.

AIN

VIN

R2

+

–

VBIAS

C1

C2

R1

TLC876

Figure 14. AC-Coupled Inputs