STM32L010RB datasheet(14/89 Pages) STMICROELECTRONICS

14 / 89 page

Functional overview

STM32L010RB

14/89

DS12319 Rev 3

•

Stop mode without RTC

The Stop mode achieves the lowest power consumption while retaining the RAM and

LSE crystal oscillator are disabled.

Some peripherals featuring wakeup capability can enable the HSI RC during Stop

mode to detect their wakeup condition.

The voltage regulator is in Low-power mode. The device can be woken up from Stop

mode by any of the EXTI line. In 3.5 µs, the processor serves the interrupt or resume

the code. The EXTI line source can be any GPIO. It can also be wakened by the

USART/I2C/LPUART/LPTIM wakeup events.

•

Standby mode with RTC

The Standby mode is used to achieve the lowest power consumption and real time

clock. The internal voltage regulator is switched off so that the entire VCORE domain is

powered off. The PLL, MSI RC, HSE and HSI RC oscillators are also switched off. The

LSE or LSI is still running. After entering Standby mode, the RAM and register contents

are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI,

LSE Crystal 32 kHz oscillator, RCC_CSR register).

The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG

reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),

RTC tamper event, RTC timestamp event or RTC wakeup event occurs.

•

Standby mode without RTC

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire VCORE domain is powered off. The

PLL, MSI RC, HSI and LSI RC, HSE and LSE crystal oscillator are also switched off.

After entering Standby mode, the RAM and register contents are lost except for

registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32 kHz

oscillator, RCC_CSR register).

The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising

edge on one of the three WKUP pin occurs.

Note:

The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by

entering Stop or Standby mode.

For power supply voltage range 1.8 V-2.0 V, CPU frequency changes from initial to final

must respect the condition: fCPU initial <4fCPU initial. It must also respect 5 µs delay between

two changes. For example, switch from 4.2 MHz to 32 MHz can be split in switch from

4.2 MHz to 16 MHz, wait 5 µs, then switch from 16 MHz to 32 MHz.

Table 2. CPU frequency range depending on dynamic voltage scaling

CPU frequency range (number of wait state)

Dynamic voltage scaling range

16 MHz to 32 MHz (1ws) - 32 kHz to 16 MHz (0ws)

Range 1

8 MHz to 16 MHz (1ws) - 32 kHz to 8 MHz (0ws)

Range 2

32 kHz to 4.2 MHz (0ws)

Range 3

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