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M50FW040 Arkusz danych(PDF) 39 Page - STMicroelectronics |
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M50FW040 Arkusz danych(HTML) 39 Page - STMicroelectronics |
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39 / 53 page ![]() M50FW040 DC and AC parameters 39/53 1. Sampled only, not 100% tested. 2. Input leakage currents include High-Z output leakage for all bidirectional buffers with tri-state outputs. Figure 10. FWH interface clock waveform 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed by design rather than tested. Refer to PCI Specification. ICC5 (1) Supply Current (Program/Erase) A/A Mux Program/Erase Controller Active 20 mA IPP VPP Supply Current (Read/Standby) VPP > VCC 400 µA IPP1 (1) VPP Supply Current (Program/Erase active) VPP = VCC 40 mA VPP = 12V ± 5% 15 mA Table 19. FWH interface clock characteristics Symbol Parameter Test Condition Value Unit tCYC CLK Cycle Time(1) Min 30 ns tHIGH CLK High Time Min 11 ns tLOW CLK Low Time Min 11 ns CLK Slew Rate peak to peak Min 1 V/ns Max 4 V/ns Table 18. DC characteristics (continued) Symbol Parameter Interface Test Condition Min Max Unit AI03403 tHIGH tLOW 0.6 VCC tCYC 0.5 VCC 0.4 VCC 0.3 VCC 0.2 VCC 0.4 VCC, p-to-p (minimum) |
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