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M50FW040 Arkusz danych(PDF) 47 Page - STMicroelectronics |
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M50FW040 Arkusz danych(HTML) 47 Page - STMicroelectronics |
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47 / 53 page ![]() M50FW040 Part numbering 47/53 11 Part numbering Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Table 27. Ordering information scheme Example: M50FW040 K 5 T G Device Type M50 Architecture F = Firmware Hub Interface Operating Voltage W = 3V to 3.6V Device Function 040 = 4 Mbit (x8), Uniform Block Package K = PLCC32 NB = TSOP32 (8 x 14mm)(1) 1. Devices delivered in this package are Not Recommended for New Design. N = TSOP40: 10 x 20 mm(1) Device Grade 5 = Temperature range –20 to 85 °C. Device tested with standard test flow Option blank = Standard Packing T = Tape & Reel Packing Plating Technology P or G = ECOPACK® (RoHs compliant) |
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