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WM8591GEDS/RV Arkusz danych(PDF) 49 Page - Wolfson Microelectronics plc

Numer części WM8591GEDS/RV
Szczegółowy opis  24-bit, 192kHz Stereo CODEC
PDF  51 Pages
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Producent  WOLFSON [Wolfson Microelectronics plc]
Strona internetowa  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8591GEDS/RV Arkusz danych(HTML) 49 Page - Wolfson Microelectronics plc

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Production Data
WM8591
w
PD Rev 4.0 December 2005
49
USE OF ADC/DAC SYNCHRONIZER
When operating the ADC and DAC simultaneously, the ADC/DAC synchronizer should be configured
to optimise internal clock phasing and device performance. The synchronizer is controlled by
registers R11 and R28 and recommended settings are described in Table 14.
In order for the clock synchronizer to operate, DAC_MCLK and ADC_MCLK must be phase locked
with coincident clock edges.
CONFIGURATION
REGISTER SETTINGS
DAC fs
(kHz)
DAC MCLK
RATE
ADC fs
(kHz)
ADC MCLK
RATE
48
768fs
48
384fs
1
1
1
*
0
0
0
96
384fs
48
384fs
1
1
1
*
0
0
0
32
1152fs
48
384fs
0
0
0
0
0
1
**
44.1
768fs
48
384fs
0
0
0
0
0
0
48
256fs
48
256fs
0
1
1
*
1
0
0
48
512fs
48
256fs
0
1
0
1
1
0
48
512fs
48
256fs
0
1
1
*
1
0
0
96
256fs
48
256fs
0
1
1
*
1
0
0
32
768fs
48
256fs
0
0
0
0
0
0
Table 14 Synchronizer Configurations
* In those modes where ADCMCLK2DAC is set, the DAC is driven by the clock signal applied to the
ADC_MCLK pin. If the DAC is operated in Master mode, the DACRATE bits (R12 [6:4]) must be set
to match the ADC_MCLK rate.
** In those modes where DACMCLK2ADC is set, the ADC is driven by the clock signal applied to the
DAC_MCLK pin. If the ADC is operated in Master mode, the ADCRATE bits (R12 [2:0]) must be set
to match the DAC_MCLK rate.



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