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WM8591GEDS/RV Arkusz danych(PDF) 29 Page - Wolfson Microelectronics plc |
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WM8591GEDS/RV Arkusz danych(HTML) 29 Page - Wolfson Microelectronics plc |
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29 / 51 page ![]() Production Data WM8591 w PD Rev 4.0 December 2005 29 DAC DIGITAL VOLUME CONTROL The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 LDA[7:0] 11111111 (0dB) Digital Attenuation data for Left channel DACL in 0.5dB steps. See Table 11 R3 (03h) 0000011 Digital Attenuation DACL 8 UPDATED Not latched Controls simultaneous update of Attenuation Latches 0: Store LDA in intermediate latch (no change to output) 1: Store LDA and update attenuation on both channels 7:0 RDA[6:0] 11111111 (0dB) Digital Attenuation data for Right channel DACR in 0.5dB steps. See Table 11 R4 (04h) 0000100 Digital Attenuation DACR 8 UPDATED Not latched Controls simultaneous update of Attenuation Latches 0: Store RDA in intermediate latch (no change to output) 1: Store RDA and update attenuation on both channels. 7:0 MDA[7:0] 11111111 (0dB) Digital Attenuation data for DAC channels in 0.5dB steps. See Table 11 R5 (05h) 0000101 Master Digital Attenuation (both channels) 8 UPDATED Not latched Controls simultaneous update of Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on channels. The volume update circuit of the WM8591 has two registers LDA and RDA. These can be accessed individually by writing to registers R3 and R4, or simultaneously by writing to R5 (MDA - Master Digital Attenuation). Writing to R5 will overwrite the contents of R3 and R4. There is no separate MDA register. L/RDA[7:0] ATTENUATION LEVEL 00(hex) - ∞ dB (mute) 01(hex) -127dB : : : : : : FE(hex) -0.5dB FF(hex) 0dB Table 11 Digital Volume Control Attenuation Levels The digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. This is enabled by control bit DZCEN. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R7 (07h) 0000111 DAC Control 0 DZCEN 0 DAC Digital Volume Zero Cross Enable: 0: Zero cross detect disabled 1: Zero cross detect enabled DAC OUTPUT PHASE The DAC Phase control word determines whether the output of the DAC is non-inverted or inverted REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION Bit DAC Phase 0 DACL 1 = invert R6 (06h) 0000110 DAC Phase 1:0 PHASE [1:0] 00 1 DACR 1 = invert |
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