WM8591GEDSSLASHRV datasheet(18/51 Pages) WOLFSON

18 / 51 page

WM8591

Production Data

PD Rev 4.0 December 2005

In a real application the designer is unlikely to have control of the relative power up sequence of

AVDD and DVDD. Using the POR circuit to monitor VMID ensures a reasonable delay between

applying power to the device and Device Ready.

Figure 8 and Figure 9 show typical power up scenarios in a real system. Both AVDD and DVDD must

be established and VMID must have reached the threshold Vporr before the device is ready and can

be written to. Any writes to the device before Device Ready will be ignored.

Figure 8 shows DVDD powering up before AVDD. Figure 9 shows AVDD powering up before DVDD.

In both cases, the time from applying power to Device Ready is dominated by the charge time of

VMID.

A 10uF cap is recommended for decoupling on VMID. The charge time for VMID will dominate the

time required for the device to become ready after power is applied. The time required for VMID to

reach the threshold is a function of the VMID resistor string and the decoupling capacitor. The

Resistor string has an typical equivalent resistance of 50kohm (+/-20%). Assuming a 10uF capacitor,

the time required for VMID to reach threshold of 1V is approx 110ms.

DIGITAL AUDIO INTERFACE

MASTER AND SLAVE MODES

The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In

both Master and Slave modes DIN is always an input to the WM8591 and DOUT is always an output.

The default for the DAC is Slave mode, and the default for the ADC is Master mode.

In Slave mode (MS=0) ADCLRC, DACLRC, ADCBCLK and DACBCLK are inputs to the WM8591

(Figure 10). DIN and DACLRC are sampled by the WM8591 on the rising edge of DACBCLK,

ADCLRC is sampled on the rising edge of ADCBCLK. ADC data is output on DOUT and changes on

the falling edge of ADCBCLK. By setting control bits ADCBCP or DACBCP the polarity of ADCBCLK

and DACBCLK may be reversed so that DIN and DACLRC are sampled on the falling edge of

DACBCLK, ADCLRC is sampled on the falling edge of ADCBCLK and DOUT changes on the rising

edge of ADCBCLK.

Figure 10 Slave Mode

In Master mode (MS=1) ADCLRC, DACLRC, ADCBCLK and DACBCLK are outputs from the

WM8591 (Figure 11), and these pins should not be driven by external circuitry. ADCLRC, DACLRC,

ADCBCLK and DACBCLK are generated by the WM8591. DIN is sampled by the WM8591 on the

rising edge of DACBCLK so the controller must output DAC data that changes on the falling edge of

DACBCLK. ADC data is output on DOUT and changes on the falling edge of ADCBCLK. By setting

control bits ADCBCP and DACBCP, the polarity of ADCBCLK and DACBCLK may be reversed so

that DIN is sampled on the falling edge of DACBCLK and DOUT changes on the rising edge of

ADCBCLK.

ADCBCLK

DOUT

ADCLRC

DIN

DACLRC

WM8591

CODEC

DVD

Controller

DACBCLK

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