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AM29PDL128G Arkusz danych(PDF) 43 Page - Advanced Micro Devices

Numer części AM29PDL128G
Szczegółowy opis  128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIOTM Control
PDF  71 Pages
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Producent  AMD [Advanced Micro Devices]
Strona internetowa  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM29PDL128G Arkusz danych(HTML) 43 Page - Advanced Micro Devices

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Am29PDL128G
October 28, 2004
P R E L IM IN A R Y
Command Definitions Tables
Legend:
BA = Address of bank switching to autoselect mode, bypass mode, or
erase operation. Determined by A21:A19, see Table 4 and Table 5 for
more details.
PA = Program Address (A21:A0). Addresses latch on falling edge of
WE# or CE# pulse, whichever happens later.
PD = Program Data (DQ15:DQ0) written to location PA. Data latches
on rising edge of WE# or CE# pulse, whichever happens first.
RA = Read Address (A21:A0).
RD = Read Data (DQ15:DQ0) from location RA.
SA = Sector Address (A21:A12) for verifying (in autoselect mode) or
erasing.
WD = Write Data. See “Configuration Register” definition for specific
write data. Data latched on rising edge of WE#.
X = Don’t care
Notes:
1.
See Table 1 for description of bus operations.
2.
All values are in hexadecimal.
3.
Shaded cells in the able denote read cycles. All other cycles are
write operations.
4.
During unlock and command cycles, when lower address bits are
555 or 2AAh as shown in the table, address bits higher than A11
(except where BA is required) and data bits higher than DQ7 are
don’t cares.
5.
No unlock or command cycles required when bank is reading
array data.
6.
Reset command is required to return to reading array (or to
erase-suspend-read mode if previously in Erase Suspend) when
bank is in autoselect mode, or if DQ5 goes high (while bank is
providing status information).
7.
Cycle 4 of autoselect command sequence is a read cycle. See
“Autoselect Command Sequence” on page 35 for more
information.
8.
The data is 80h for factory locked and 00h for not factory locked.
9.
The data is 00h for an unprotected sector group and 01h for a
protected sector group.
10. Device ID must be read across cycles 4, 5, and 6.
11. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Program/Erase Suspend mode.
Program/Erase Suspend command is valid only during a sector
erase operation, and requires bank address.
12. Program/Erase Resume command valid only during Erase
Suspend mode, and requires bank address.
13. Command valid when device is ready to read array data or when
device is in autoselect mode.
14. ACC must be at V
ID during entire operation of command.
15. Unlock Bypass Entry command is required prior to any Unlock
Bypass operation. Unlock Bypass Reset command is required to
return to reading array.
Table 14.
Memory Array Command Definitions (x32 Mode)
Command (Notes)
Bus Cycles (Notes 1, 2, 3, and 4)
Addr Data Addr Data Addr Data
Addr
Data
Addr
Data
Addr
Data
Read (5)1
RA
RD
Reset (6)1
XXX
F0
Autoselect
(Note 7)
Manufacturer ID
4
555
AA
2AA
55
555
90
(BA)X00
01
Device ID (10)
6
555
AA
2AA
55
555
90
(BA)X01
7E
(BA)X0E
0D
(BA)X0F
00
SecSi Sector
Factory Protect (8)
4
555
AA
2AA
55
555
90
X03
(Note 8)
Sector Group
Protect Verify (9)
4
555
AA
2AA
55
555
90
SA02
XX00/
XX01
Program
4
555
AA
2AA
55
555
A0
PA
PD
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Program/Erase Suspend (11)
1
BA
B0
Program/Erase Resume (12)1
BA
30
CFI Query (13)
1
55
98
Accelerated Program (14)
2
XX
A0
PA
PD
Unlock Bypass Entry (15)
3
555
AA
2AA
55
555
20
Unlock Bypass Program (15)
2
XX
A0
PA
PD
Unlock Bypass Erase (15)
2
XX
80
XX
10
Unlock Bypass CFI (13, 15)1
XX
98
Unlock Bypass Reset (15)2
XXX
90
XX
00



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