AM29PDL128G datasheet(12/71 Pages) AMD

12 / 71 page

October 28, 2004

Am29PDL128G

P R E L IM IN A R Y

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels required, and the resulting out-

put. The following subsections describe each of these

operations in further detail.

Table 1.

Am29PDL128G Device Bus Operations

Legend: L = Logic Low = V

IL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,

IN = Address In, DIN = Data In, DOUT = Data Out

Notes:

1. Addresses are A21–A0 in double word mode (WORD# = V

IH), A21–A-1 in word mode (WORD# = VIL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector Protection”

on page 24.

Word/Double Word Configuration

The WORD# pin controls whether the device data I/O

pins operate in the word or double word configuration.

If the WORD# pin is set at V

IH, the device is in double

word configuration, DQ31–DQ0 are active and con-

trolled by CE# and OE#.

If the WORD# pin is set at V

IL, the device is in word

configuration, and only data I/O pins DQ15–DQ0 are

active and controlled by CE# and OE#. The data I/O

pins DQ30–DQ16 are tri-stated, and the DQ31 pin is

used as an input for the least significant address bit

(LSB) function, which is named A-1.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V

IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V

IH. The WORD# pin deter mines

whether the device outputs array data in words or dou-

ble words.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. Each bank remains

enabled for read access until the command register

contents are altered.

Refer to the AC Read-Only Operations table on

page 53 for timing specifications and to Table 12 for

the timing diagram. I

CC1 in the DC Characteristics table

represents the active current specification for reading

array data.

Random Read (Non-Page Read)

Address access time (t

ACC) is equal to the delay from

stable addresses to valid output data. The chip enable

access time (t

CE) is the delay from the stable ad-

dresses and stable CE# to valid data at the output in-

puts. The output enable access time is the delay from

the falling edge of the OE# to valid data at the output

Operation

CE#

OE#

WE#

RESET#

WP#

Addresses

(Note 1)

DQ31–DQ16

DQ15–

DQ0

WORD#

= V

WORD#

= V

Read

AIN

DOUT

DQ30–DQ16 =

High-Z, DQ31 = A-1

DOUT

Write

Standby

VCC ±

0.3 V

VCC ±

0.3 V

High-Z

Output Disable

High-Z

Reset

High-Z

Temporary Sector

Unprotect (High Voltage)

VID

XAIN

DIN

XDIN

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