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TCS3530 Arkusz danych(PDF) 80 Page - OSRAM GmbH |
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TCS3530 Arkusz danych(HTML) 80 Page - OSRAM GmbH |
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80 / 106 page ![]() Datasheet, Public Page 79 [v3-00] 2023-Jun-23 Document Feedback TCS3530 − Register Overview VSYNC_CONTROL Register Figure 115: VSYNC_CONTROL Note(s): 1. Return to the Register Map (0xF1). VSYNC_CFG Register Figure 116: VSYNC_CFG Addr: 0xF1 VSYNC_CONTROL Bit Field Reset Type Bit Description 7:1 Reserved 0 0 SW_VSYNC_TRIGGER 0 R/W Trigger Software vsync Pulse. In case if vsync_mode is 1, this register can be written to 1 to trigger a vsync from I²C/I3C side. If one knows the exact time between two such I²C/I3C writings, the oscillator offset can be calculated by using the resulting value in vsync_ trigger. Addr: 0xF2 VSYNC_CFG Bit Field Default Access Bit Description 7:6 OSC_CALIB_MODE 0 R/W Oscillator calibration mode register Value ID Meaning 0 osccal_ disable no autmatic oscillator calibration is done 1 osccal_ after_pon if pon goes to 1 or after each vsync_lost goes 0 an oscillator calibration is done once not during measurement 2 osccal_ always_on oscillator calibration is done always if possible, not during measurement and not if vsync_lost is detected 3 osccal_ reserved if set to 3, osccal is also not starting |
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