TCS3530 datasheet(27/106 Pages) OSRAM

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[v3-00] 2023-Jun-23

TCS3530 − Register O ver view

OSCEN Register

Figure 23:

OSCEN

Note(s):

1. Return to the Register Map (0x7F).

ENABLE Register

Figure 24:

ENABLE

Note(s):

1. Return to the Register Map (0x80).

Addr: 0x7F

OSCEN

Bit

Field

Reset

Type

Bit Description

7:3

Reserved

2PON_INIT

This bit is “1” after power on for about 300μs. The device

will not respond to any I²C/I3C bus traffic. It can be used

for power on polling.

OSCEN_STATUS

Oscillator Enable. The I²C/I3C access to all clocked

registers is disabled, if the oscillator is turned off.

0OSCEN

R/W

Oscillator Enable. Writing a “1” activates the oscillator.

Writing a “0” disables the oscillator.

Note, that “PON” in register 0x80 also indicates when the

oscillator is on and the internal state-machine is enabled

and operating. This operation is temporarily disabled by

“SAI” in register 0xA1 while the oscillator keeps running

(e.g. for single-shot measurements).

Addr: 0x80

ENABLE

Bit

Field

Reset

Type

Bit Description

7Reserved

6FDEN

R/W

Flicker Detection Enable. Writing a “1” activates flicker

detection. Writing a “0” disables flicker detection.

5:2

Reserved

1AEN

R/W

ALS Enable. Writing a “1” enables ALS/Color. Writing a “0”

disables ALS/Color.

0PON

R/W

Power ON. When asserted, the internal oscillator is activated,

allowing timers and ADC channels to operate. Writing a “0”

disables the oscillator and clears PEN, and AEN. Only set this

bit after all other registers have been initialized by the host.

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