TCS3530 datasheet(55/106 Pages) OSRAM

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[v3-00] 2023-Jun-23

TCS3530 − Register O ver view

SIEN Register

Figure 65:

SIEN

Note(s):

1. Return to the Register Map (0xBB).

CONTROL Register

Figure 66:

CONTROL

Note(s):

1. Return to the Register Map (0xBC).

Addr: 0xBB

SIEN

Bit

Field

Reset

Type

Bit Description

7:3

Reserved

SIEN_AUX

R/W

Auxiliary System Interrupt Enable. Setting this bit will

allow a system interrupt SINT as soon as an auxiliary

interrupt occurs. Please see SINT_AUX for further

information.

SIEN_

MEASUREMENT_

SEQUENCER

0R/W

Measurement Sequencer Interrupt Enable. Setting this

bit will allow a system interrupt SINT as soon as invoked

by a measurement sequencer event. Please see SINT_

MEASUREMENT_SEQUENCER for further information

SIEN_VSYNC

R/W

Vsync Interrupt Enable. Setting this bit will allow a

system interrupt SINT as soon as soon as a vysnc interrupt

occurs. Please see SINT_VSYNC for further information.

Addr: 0xBC

CONTROL

Bit

Field

Reset

Type

Bit Description

7:2

Reserved

1FIFO_CLR

R/W

Setting this bit will clear the FIFO, as well as FINT, FIFO_

FULL, FIFO_OVERFLOW, FIFO_UNDERFLOW and FIFO_LVL.

CLEAR_SAI_

ACTIVE

0R/W

Setting this bit will clear the Sleep After Interrupt Active

SAI_ACTIVE and start measurements if enabled.

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