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TSL2521 Arkusz danych(PDF) 37 Page - OSRAM GmbH |
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TSL2521 Arkusz danych(HTML) 37 Page - OSRAM GmbH |
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37 / 81 page ![]() Page 36 Datasheet, Public Document Feedback [v3-00] 2022-Dec-21 TSL2521 − Register O ver view CFG3 Register Figure 43: CFG3 Note(s): 1. Return to the Register Map (0xA4). Addr: 0xA4 CFG3 Bit Field Reset Type Bit Description 7:6 Reserved 0 5:4 INT_PINMAP 0 R/W Interrupt Pin Mapping. Defines internal signal which is routed to the external INT pin. 00: Default, INTERRUPT 01: AINT_HYST_STATE 10: Reserved, do not use 11: Reserved, do not use 3:2 Reserved 0 1:0 VSYNC_GPIO_PINMAP 0 R/W Vsync/GPIO Pin Mapping. Defines internal signal which is routed to the external VSYNC/GPIO pin. 00: Default, VSYNC_GPIO_OUT 01: AINT_HYST_STATE 10: Reserved, do not use 11: Reserved, do not use |
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