MSC8144 datasheet(75/80 Pages) FREESCALE

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Hardware Design Considerations

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1

Freescale Semiconductor

3.3.8

Miscellaneous Pins

Table 68 lists the board connections for the pins if they are required by the system design. Table 68 assumes that the alternate

function of the specified pin is not used. If the alternate function is used, connect that pin as required to support the selected

function.

Note:

For details on configuration, see the MSC8144 Reference Manual. For additional information, refer to the MSC8144

Design Checklist (AN3202).

3.4

External DDR SDRAM Selection

TBD

Table 68. Connectivity of Individual Pins When They Are Not Required

Signal Name

Pin Connection

CLKOUT

EE0

GND

EE1

GPIO[0–31]

SCL

See the GPIO connectivity guidelines in this table.

SDA

See the GPIO connectivity guidelines in this table.

INT_OUT

IRQ[0–15]

See the GPIO connectivity guidelines in this table.

NMI

VDDIO

NMI_OUT

RC[0–16]

GND

RC_LDF

STOP_BS

GND

TCK

GND

TDI

GND

TDO

TMR[0–4]

See the GPIO connectivity guidelines in this table.

TMS

GND

TRST

GND

URXD

See the GPIO connectivity guidelines in this table.

UTXD

See the GPIO connectivity guidelines in this table.

VDDIO

3.3 V

Note:

When using I/O multiplexing mode 5 or 6, tie the TDM7TSYN/PCI_AD4 signal (ball number AC9) to GND.

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