PIC12F683_07 datasheet(90/176 Pages) MICROCHIP

90 / 176 page

PIC12F683

DS41211D-page 88

12.3.6

TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows:

• PWRT time-out is invoked after POR has expired.

• OST is activated after the PWRT time-out has

expired.

The total time-out will vary based on oscillator

configuration and PWRTE bit status. For example, in EC

mode with PWRTE bit erased (PWRT disabled), there

will be no time-out at all. Figure 12-4, Figure 12-5 and

Figure 12-6 depict time-out sequences. The device can

execute code from the INTOSC while OST is active by

enabling Two-Speed Start-up or Fail-Safe Monitor (see

Section 3.7.2 “Two-Speed Start-up Sequence” and

Section 3.8 “Fail-Safe Clock Monitor”).

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then,

bringing MCLR high will begin execution immediately

(see Figure 12-5). This is useful for testing purposes or

to synchronize more than one PIC12F683 device

operating in parallel.

Table 12-5 shows the Reset conditions for some

special registers, while Table 12-4 shows the Reset

conditions for all the registers.

12.3.7

POWER CONTROL (PCON)

The Power Control register PCON (address 8Eh) has

two Status bits to indicate what type of Reset occurred

last.

Bit 0 is BOR (Brown-out). BOR is unknown on

Power-on Reset. It must then be set by the user and

checked on subsequent Resets to see if BOR = 0,

indicating that a Brown-out has occurred. The BOR

Status bit is a “don’t care” and is not necessarily

predictable

the

brown-out

circuit

disabled

(BOREN<1:0>

= 00 in the Configuration Word

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaffected otherwise. The user must write a

‘1’ to this bit following a Power-on Reset. On a subse-

quent Reset, if POR is ‘0’, it will indicate that a

Power-on Reset has occurred (i.e., VDD may have

gone too low).

For more information, see Section 4.2.4 “Ultra

Low-Power

Wake-up”

and

Section 12.3.4

“Brown-Out Reset (BOR)”.

TABLE 12-1:

TIME-OUT IN VARIOUS SITUATIONS

TABLE 12-2:

STATUS/PCON BITS AND THEIR SIGNIFICANCE

TABLE 12-3:

SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET

Oscillator Configuration

Power-up

Brown-out Reset

Wake-up from

Sleep

PWRTE = 0

PWRTE = 1

PWRTE = 0

PWRTE = 1

XT, HS, LP

TPWRT + 1024 •

TOSC

1024 • TOSC

TPWRT + 1024 •

TOSC

1024 • TOSC

RC, EC, INTOSC

TPWRT

—TPWRT

——

POR

BOR

Condition

0x11

Power-on Reset

u011

Brown-out Reset

uu0u

WDT Reset

uu00

WDT Wake-up

uuuu

MCLR Reset during normal operation

uu10

MCLR Reset during Sleep

Legend: u = unchanged, x = unknown

Name

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets(1)

CONFIG(2)

BOREN1

BOREN0

CPD

MCLRE

PWRTE

WDTE

FOSC2

FOSC1

FOSC0

—

PCON

—

ULPWUE SBOREN

—

—POR

BOR

--01 --qq

--0u --uu

STATUS

IRP

RP1

RP0

0001 1xxx

000q quuu

Legend:

= unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR.

Note

Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

See Configuration Word register (Register 12-1) for operation of all register bits.

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