PIC12F683_07 datasheet(96/176 Pages) MICROCHIP

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PIC12F683

DS41211D-page 94

FIGURE 12-8:

INT PIN INTERRUPT TIMING

TABLE 12-6:

SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON

GIE

PEIE

T0IE

INTE

GPIE

T0IF

INTF

GPIF

0000 0000 0000 0000

IOC

—

IOC5

IOC4

IOC3

IOC2

IOC1

IOC0

--00 0000 --00 0000

PIR1

EEIF

ADIF

CCP1IF

—

CMIF

OSFIF

TMR2IF

TMR1IF

000- 0000 000- 0000

PIE1

EEIE

ADIE

CCP1IE

—

CMIE

OSFIE

TMR2IE

TMR1IE

000- 0000 000- 0000

Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition.

Shaded cells are not used by the interrupt module.

OSC1

CLKOUT

INT pin

INTF flag

(INTCON reg.)

GIE bit

(INTCON reg.)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

Interrupt Latency

PC + 1

0004h

0005h

Inst (0004h)

Inst (0005h)

Dummy Cycle

Inst (PC)

Inst (PC + 1)

Inst (PC – 1)

Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note 1:

INTF flag is sampled here (every Q1).

Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency

is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

CLKOUT is available only in INTOSC and RC Oscillator modes.

For minimum width of INT pulse, refer to AC specifications in Section 15.0 “Electrical Specifications”.

INTF is enabled to be set any time during the Q4-Q1 cycles.

(1)

(2)

(3)

(4)

(5)

(1)

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