PIC12F683_07 datasheet(98/176 Pages) MICROCHIP

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PIC12F683

DS41211D-page 96

12.6

Watchdog Timer (WDT)

The WDT has the following features:

• Operates from the LFINTOSC (31 kHz)

• Contains a 16-bit prescaler

• Shares an 8-bit prescaler with Timer0

• Time-out period is from 1 ms to 268 seconds

• Configuration bit and software controlled

WDT is cleared under certain conditions described in

Table 12-7.

12.6.1

WDT OSCILLATOR

The WDT derives its time base from the 31 kHz

LFINTOSC. The LTS bit of the OSCCON register does

not reflect that the LFINTOSC is enabled.

The value of WDTCON is ‘---0 1000’ on all Resets.

This gives a nominal time base of 17 ms.

12.6.2

WDT CONTROL

The WDTE bit is located in the Configuration Word

When the WDTE bit in the Configuration Word register

is set, the SWDTEN bit of the WDTCON register has no

effect. If WDTE is clear, then the SWDTEN bit can be

used to enable and disable the WDT. Setting the bit will

enable it and clearing the bit will disable it.

The PSA and PS<2:0> bits of the OPTION register

have the same function as in previous versions of the

PIC12F683

Family

microcontrollers.

See

Section 5.0 “Timer0 Module” for more information.

FIGURE 12-9:

WATCHDOG TIMER BLOCK DIAGRAM

TABLE 12-7:

WDT STATUS

Note:

When the Oscillator Start-up Timer (OST)

is invoked, the WDT is held in Reset,

because the WDT Ripple Counter is used

by the OST to perform the oscillator delay

count. When the OST count has expired,

the WDT will begin counting (if enabled).

Conditions

WDT

WDTE = 0

Cleared

CLRWDT

Command

Oscillator Fail Detected

Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Cleared until the end of OST

31 kHz

PSA

16-bit WDT Prescaler

From Timer0 Clock Source

Prescaler(1)

PS<2:0>

PSA

WDT Time-out

To Timer0

WDTPS<3:0>

WDTE from Configuration Word register

SWDTEN from WDTCON

LFINTOSC Clock

Note

This is the shared Timer0/WDT prescaler. See Section 5.0 “Timer0 Module” for more information.

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