S25FL256SDPNFAQ datasheet(51/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

Page 50 of 148

S25FL128S/S25FL256S

7.5.2

Configuration Register 1 (CR1)

Related Commands: Read Configuration Register (RDCR 35h), Write Registers (WRR 01h). The Configuration Register bits can be

changed using the WRR command with sixteen input cycles.

The configuration register controls certain interface and data protection functions.

Latency Code (LC) CR1[7:6]:

The Latency Code selects the number of mode and dummy cycles between the end of address and

the start of read data output for all read commands.

Some read commands send mode bits following the address to indicate that the next command will be of the same type with an

implied, rather than an explicit, instruction. The next command thus does not provide an instruction byte, only a new address and

mode bits. This reduces the time needed to send each command when the same command type is repeated in a sequence of

commands.

Dummy cycles provide additional latency that is needed to complete the initial read access of the flash array before data can be

returned to the host system. Some read commands require additional latency cycles as the SCK frequency is increased.

The following latency code tables provide different latency settings that are configured by Cypress. The High Performance versus

the Enhanced High Performance settings are selected by the ordering part number.

Where mode or latency (dummy) cycles are shown in the tables as a dash, that read command is not supported at the frequency

shown. Read is supported only up to 50 MHz but the same latency value is assigned in each latency code and the command may be

used when the device is operated at

 50 MHz with any latency code setting. Similarly, only the Fast Read command is supported

up to 133 MHz but the same 10b latency code is used for Fast Read up to 133 MHz and for the other dual and quad read commands

up to 104 MHz. It is not necessary to change the latency code from a higher to a lower frequency when operating at lower

frequencies where a particular command is supported. The latency code values for a higher frequency can be used for accesses at

lower frequencies.

The High Performance settings provide latency options that are the same or faster than alternate source SPI memories. These

settings provide mode bits only for the Quad I/O Read command.

The Enhanced High Performance settings similarly provide latency options the same or faster than additional alternate source SPI

memories and adds mode bits for the Dual I/O Read, DDR Fast Read, and DDR Dual I/O Read commands.

Table 25. Configuration Register 1(CR1)

Bits

Field Name

Function

Type

Default

State

Description

LC1

Latency Code

Non-Volatile

Selects number of initial read latency cycles

See Latency Code Tables

LC0

TBPROT

Configures Start of

Block Protection

OTP

1 = BP starts at bottom (Low address)

0 = BP starts at top (High address)

RFU

OTP

Reserved for Future Use

BPNV

Configures BP2-0 in

Status Register

OTP

1 = Volatile

0 = Non-Volatile

TBPARM

Configures Parame-

ter Sectors location

OTP

1 = 4-kB physical sectors at top, (high address)

0 = 4-kB physical sectors at bottom (Low address)

RFU in uniform sector devices

QUAD

Puts the device into

Quad I/O operation

Non-Volatile

1 = Quad

0 = Dual or Serial

FREEZE

Lock current state of

BP2-0 bits in Status

and TBPARM in

Configuration Regis-

ter, and OTP regions

Volatile

1 = Block Protection and OTP locked

0 = Block Protection and OTP un-locked

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