S25FL256SDPNFAQ datasheet(80/149 Pages) CYPRESS

80 / 149 page

Document Number: 001-98283 Rev. *M

Page 79 of 148

S25FL128S/S25FL256S

9.3.10 Clear Status Register (CLSR 30h)

The Clear Status Register command resets bit SR1[5] (Erase Fail Flag) and bit SR1[6] (Program Fail Flag). It is not necessary to set

the WEL bit before the Clear SR command is executed. The Clear SR command will be accepted even when the device remains

busy with WIP set to 1, as the device does remain busy when either error bit is set. The WEL bit will be unchanged after this

command is executed.

Figure 53. Clear Status Register (CLSR) Command Sequence

9.3.11 ECC Status Register Read (ECCRD 18h)

To read the ECC Status Register, the command is followed by the ECC unit (32 bit) address, the four least significant bits (LSB) of

address must be set to zero. This is followed by eight dummy cycles. Then the 8-bit contents of the ECC Register, for the ECC unit

selected, are shifted out on SO 16 times, once for each byte in the ECC Unit. If CS# remains low the next ECC unit status is sent

through SO 16 times, once for each byte in the ECC Unit, this continues until CS# goes high. The maximum operating clock

frequency for the ECC READ command is 133 MHz. See Section 9.5.1.1 Automatic ECC on page 100 for details on ECC unit.

Figure 54. ECC Status Register Read Command Sequence

Instruction

SCK

210

039

Instruction

32-Bit

Address

765

Dummy Byte

DATA OUT 1

DATA OUT 2

SCK

MSB

High Impedance

MSB

CS#

765

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