S25FL256SDPNFAQ datasheet(66/149 Pages) CYPRESS

66 / 149 page

Document Number: 001-98283 Rev. *M

Page 65 of 148

S25FL128S/S25FL256S



Although host software in some cases is used to directly control the SPI interface signals, the hardware interfaces of the host

system and the memory device generally handle the details of signal relationships and timing. For this reason, signal relationships

and timing are not covered in detail within this software interface focused section of the document. Instead, the focus is on the

logical sequence of bits transferred in each command rather than the signal timing and relationships. Following are some general

signal relationship descriptions to keep in mind. For additional information on the bit level format and signal timing relationships of

commands, see Section 3.2 Command Protocol on page 14.

– The host always controls the Chip Select (CS#), Serial Clock (SCK), and Serial Input (SI) - SI for single bit wide transfers. The

memory drives Serial Output (SO) for single bit read transfers. The host and memory alternately drive the IO0-IO3

signals during Dual and Quad transfers.

– All commands begin with the host selecting the memory by driving CS# low before the first rising edge of SCK. CS# is kept

low throughout a command and when CS# is returned high the command ends. Generally, CS# remains low for 8-bit transfer

multiples to transfer byte granularity information. Some commands will not be accepted if CS# is returned high not at an 8-bit

boundary.

9.1

Command Set Summary

9.1.1

Extended Addressing

To accommodate addressing above 128 Mb, there are three options:

1. New instructions are provided with 4-byte address, used to access up to 32 Gb of memory.

Instruction Name

Description

Code (Hex)

4FAST_READ

Read Fast (4-byte Address)

4READ

Read (4-byte Address)

4DOR

Read Dual Out (4-byte Address)

4QOR

Read Quad Out (4-byte Address)

4DIOR

Dual I/O Read (4-byte Address)

4QIOR

Quad I/O Read (4-byte Address)

4DDRFR

Read DDR Fast (4-byte Address)

4DDRDIOR

DDR Dual I/O Read (4-byte Address)

4DDRQIOR

DDR Quad I/O Read (4-byte Address)

4PP

Page Program (4-byte Address)

4QPP

Quad Page Program (4-byte Address)

4P4E

Parameter 4-kB Erase (4-byte Address)

4SE

Erase 64/256 kB (4-byte Address)

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