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S25FL256SDPNFAQ Arkusz danych(PDF) 75 Page - Cypress Semiconductor

Numer części S25FL256SDPNFAQ
Szczegółowy opis  128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte) 128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte)
PDF  149 Pages
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Producent  CYPRESS [Cypress Semiconductor]
Strona internetowa  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

S25FL256SDPNFAQ Arkusz danych(HTML) 75 Page - Cypress Semiconductor

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Document Number: 001-98283 Rev. *M
Page 74 of 148
S25FL128S/S25FL256S
9.3.2
Read Status Register-2 (RDSR2 07h)
The Read Status Register (RDSR2) command allows the Status Register-2 contents to be read from SO. The Status Register-2
contents may be read at any time, even while a program, erase, or write operation is in progress. It is possible to read the Status
Register-2 continuously by providing multiples of eight clock cycles. The status is updated for each eight cycle read. The maximum
clock frequency for the RDSR2 command is 133 MHz.
Figure 9.3 Read Status Register-2 (RDSR2) Command
9.3.3
Read Configuration Register (RDCR 35h)
The Read Configuration Register (RDCR) command allows the Configuration Register contents to be read from SO. It is possible to
read the Configuration Register continuously by providing multiples of eight clock cycles. The Configuration Register contents may
be read at any time, even while a program, erase, or write operation is in progress.
Figure 9.4 Read Configuration Register (RDCR) Command Sequence
9.3.4
Bank Register Read (BRRD 16h)
The Read the Bank Register (BRRD) command allows the Bank address Register contents to be read from SO. The instruction is
first shifted in from SI. Then the 8-bit Bank Register is shifted out on SO. It is possible to read the Bank Register continuously by
providing multiples of eight clock cycles. The maximum operating clock frequency for the BRRD command is 133 MHz.
Figure 46. Read Bank Register (BRRD) Command
1
3
210
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8
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0
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Instruction
1
32
0
765
4
SCK
SO
High Impedance
MSB
Status Register-2 Out
SI
15
18
17
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22
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20
19
1
32
0
7654
MSB
Status Register-2 Out
23
7
MSB
CS#
1
32
0
765
4
CS#
SCK
SI
SO
Phase
7
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4
3
2
1
0
7
6
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4
3
2
1
0
7
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4
3
2
1
0
Instruction
Register Read
Repeat Register Read
7
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4
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3
2
1
0
3
2
1
0
0
1
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High Impedance
High Impedance
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1
0
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2
1
0
7
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3
2
1
0
3
2
1
0
Bank Register Out
Bank Register Out
Bank Register Out
Bank Register Out
Instruction
Instruction
MSB
MSB
MSB
MSB
MSB
MSB
7
MSB
MSB
CS#
CS#
SCK
SCK
SI
SI
SO
SO



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