ST7SCR1R4 datasheet(100/102 Pages) STMICROELECTRONICS

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This limitation will be corrected in the next silicon revision. In the new revision, when a SETUP

token is received, the value loaded in the internal counter is fixed to 8 by hardware independ-

ently of the value in the CNT0RXR register.

20.3 USB BUFFER SHARED MEMORY ACCESS

Description

When fCPU is at 4 MHz, a value written in the USB buffer may be corrupted when VDD is less

than 4.4V. This limitation will be corrected in the next silicon revision.

Impact

USB buffer access cannot be guaranteed over the full VDD range when fCPU is at 4 MHz.

20.4 WDG (WATCHDOG) LIMITATIONS

In flash devices, the WDG prescaler value is not 65536 as described in Section 12.1.3 on

page 40 (Figure 25), it is actually 16.

This will be corrected in the next revision of the silicon.

20.5 SUPPLY CURRENT IN HALT MODE (SUSPEND) LIMITATIONS

The current consumption (IDD) in some devices may exceed the maximum specified in the

documentation (up to 1mA).

Workaround

Declare 200mA max. power value in the USB Configuration Descriptor.

20.5.1 VPP Pin Limitation

In the impacted flash devices, contrary to the datasheet specification (which specifies that it

must be tied to VSS), the VPP pin must be tied to VDD in operating mode. This will be fixed in

the next silicon revision .

20.6 START-UP

The ST7SCR relies on internal LVD and it may not start-up correctly if the power supply is

slow.

Workaround

Put a 1M

Ω resistor between V

DD and VSS to eliminate the offset on VDD that may cause this

power-on problem.

ST7SCR1R4 Arkusz danych(PDF) 100 Page - STMicroelectronics