ST7SCR1R4 datasheet(55/102 Pages) STMICROELECTRONICS

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ST7SCR

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12.4 SMARTCARD INTERFACE (CRD)

12.4.1 Introduction

The Smartcard Interface (CRD) provides all the re-

quired signals for acting as a smartcard interface

device.

The interface is electrically compatible with (and

certifiable to) the ISO7816, EMV, GSM and WHQL

standards.

Both synchronous (e.g. memory cards) and asyn-

chronous smartcards (e.g. microprocessor cards)

are supported.

The CRD generates the required voltages to be

applied to the smartcard lines.

The power-off sequence is managed by the CRD.

Card insertion or card removal is detected by the

CRD using a card presence switch connected to

the external CRDDET pin. If a card is removed, the

CRD automatically deactivates the smartcard us-

ing the ISO7816 deactivation sequence.

An maskable interrupt is generated when a card is

inserted or removed.

Any malfunction is reported to the microcontroller

via the Smartcard Interrupt Pending Register

(CRDIPR) and Smartcard Status (CRDSR) Regis-

ters.

12.4.2 Main features

Support for ISO 7816-3 standard

Character mode

1 transmit buffer and 1 receive buffer

4-Mhz fixed card clock

11-bit etu (elementary time unit) counter

9-bit guardtime counter

24-bit general purpose waiting time counter

Parity generation and checking

Automatic character repetition on parity error

detection in transmission mode

Automatic retry on parity error detection in

reception mode

Card

power-off

deactivation

sequence

generation

Manual mode for driving the card I/O directly for

synchronous protocols

12.4.3 Functional Description

Figure 29 gives an overview of the smartcard inter-

face.

Figure 29. Smartcard Interface Block Diagram

CLK

SEL

CRD

CLK

CRDCCR

CRD

CRD CRD

RST VCC

CRD

CRDIO

CRDC4

CRDC8

CRDRST

CRDCLK

CRDDET

UART SHIFT REGISTER

CRDRXB

CRDTXB

UART RECEIVE BUFFER

UART TRANSMIT BUFFER

CARD DETECTION

CARD INSERTION/

CRDVCC

POWER-OFF LOGIC

CLOCK

CONTROL

UART BIT

11-BIT

4 MHz

ETU COUNTER

9-BIT GUARDTIME COUNTER

24-BIT WAITING TIME COUNTER

PARITY GENERATION/CHECKING

COMMUNICATIONS CONTROL

CRD INTERRUPT

LOGIC

REMOVAL INTERRUPT

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