ST7SCR1R4 datasheet(47/102 Pages) STMICROELECTRONICS

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ST7SCR

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USB INTERFACE (Cont’d)

INTERRUPT MASK REGISTER (USBIMR)

Read/Write

Reset Value: 0000 0000 (00h)

These bits are mask bits for all the interrupt condi-

tion bits included in the USBISTR register. When-

ever one of the USBIMR bits is set, if the corre-

sponding USBISTR bit is set, and the I- bit in the

CC register is cleared, an interrupt request is gen-

erated. For an explanation of each bit, please refer

to the description of the USBISTR register.

CONTROL REGISTER (USBCTLR)

Read/Write

Reset value: 0000 0110 (06h)

Bit 7 = RSM

Resume Detected

This bit shows when a resume sequence has start-

ed on the USB port, requesting the USB interface

to wake-up from suspend state. It can be used to

determine the cause of an ESUSP event.

0: No resume sequence detected on USB

1: Resume sequence detected on USB

Bit 6 = USB_RST

USB Reset detected.

This bit shows that a reset sequence has started

on the USB. It can be used to determine the cause

of an ESUSP event (Reset sequence).

0: No reset sequence detected on USB

1: Reset sequence detected on USB

Bits [5:4] = Reserved, forced by hardware to 0.

Bit 3 = RESUME

Resume.

This bit is set by software to wake-up the Host

when the ST7 is in suspend mode.

0: Resume signal not forced

1: Resume signal forced on the USB bus.

Software should clear this bit after the appropriate

delay.

Bit 2 = PDWN

Power down.

This bit is set by software to turn off the 3.3V on-

chip voltage regulator that supplies the external

pull-up resistor and the transceiver.

0: Voltage regulator on

1: Voltage regulator off

Note: After turning on the voltage regulator, soft-

ware should allow at least 3 µs for stabilisation of

the power supply before using the USB interface.

Bit 1 = FSUSP

Force suspend mode.

This bit is set by software to enter Suspend mode.

The ST7 should also be put in Halt mode to reduce

power consumption.

0: Suspend mode inactive

1: Suspend mode active

When the hardware detects USB activity, it resets

this bit (it can also be reset by software).

Bit 0 = FRES

Force reset.

This bit is set by software to force a reset of the

USB interface, just as if a RESET sequence came

from the USB.

0: Reset not forced

1: USB interface reset forced.

The USB is held in RESET state until software

clears this bit, at which point a “USB-RESET” in-

terrupt will be generated if enabled.

CTRM

SOVR

ERRM

SUSP

ESUSP

RESET

SOFM

RSM

USB_

RST

RESU

PDWN

FSUSP

FRES

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