ST92141 datasheet(105/179 Pages) STMICROELECTRONICS

105 / 179 page

105/179

ST92141 - EXTENDED FUNCTION TIMER (EFT)

EXTENDED FUNCTION TIMER (Cont’d)

7.3.3.7 Pulse Width Modulation Mode

Pulse Width Modulation mode enables the gener-

ation of a signal with a frequency and pulse length

determined by the value of the OC1R and OC2R

registers.

The pulse width modulation mode uses the com-

plete Output Compare 1 function plus the OC2R

Procedure

To use pulse width modulation mode select the fol-

lowing in the CR1 register:

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful com-

parison with OC1R register.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful com-

parison with OC2R register.

And select the following in the CR2 register:

– Set OC1E bit: the OCMP1 pin is then dedicated

to the output compare 1 function.

– Set the PWM bit.

– Select the timer clock CC[1:0] bits (see Table 22

Clock Control Bits).

Load the OC2R register with the value corre-

sponding to the period of the signal.

Load the OC1R register with the value corre-

sponding to the length of the pulse if (OLVL1=0

and OLVL2=1).

If OLVL1=1 and OLVL2=0 the length of the pulse

is the difference between the OC2R and OC1R

registers.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

Where:

– t = Desired output compare period (seconds)

– INTCLK = Internal clock frequency

– CC1-CC0 = Timer clock prescaler

The Output Compare 2 event causes the counter

to be initialized to FFFCh (See Figure 62).

Note: After a write instruction to the OC

iHR regis-

ter, the output compare function is inhibited until

the OC

iLR register is also written.

The OCF1 and OCF2 bits cannot be set by hard-

ware in PWM mode therefore the Output Compare

interrupt is inhibited. The Input Capture interrupts

are available.

When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

Figure 62. Pulse Width Modulation Mode Timing

iR Value =

t * INTCLK

CC[1:0]

- 5

Counter

Counter is reset

to FFFCh

OCMP1 = OLVL2

Counter

= OC2R

OCMP1 = OLVL1

When

= OC1R

Pulse Width Modulation cycle

COUNTER

34E2

FFFC FFFD FFFE

2ED0 2ED1 2ED2

34E2

FFFC

OLVL2

OLVL1

OCMP1

compare2

compare1

compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

ST92141 Arkusz danych(PDF) 105 Page - STMicroelectronics

ST92141 Arkusz danych(HTML) 105 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL