t − Time=20ms/div

Layout Recommendations

Exposed Pad On DRV601RTJ Package

SGND and PGND Connections

Gain setting resistors

DRV601

SQUARE WAVE OUTPUT VOLTAGE

with

CAPACITIVE LOAD

Figure 14.

A proposed layout for the DRV601 can be seen in the DRV601EVM user's guide, SLOU215, and the Gerber files

can be downloaded on www.ti.com, open the DRV601 product folder and look in the Tools & Software folder.

The exposed metal pad on the DRV601RTJ package must be soldered down to a pad on the PCB in order to

maintain reliability. The pad on the PCB should be allowed to float and not be connected to ground or power.

Connecting this pad to power or ground prevents the device from working properly because it is connected

internally to PVSS.

The SGND and PGND pins of the DRV601 must be routed back to the decoupling capacitor separately in order

to provide proper device operation. If the SGND and PGND pins are connected directly to each other, the part

functions without risk of failure, but the noise and THD performance do not meet the specifications.

capacitive loading on these input pins and to ensure maximum stability of the DRV601. For the recommenced

PCB layout, see the DRV601EVM user guide.

10

Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): DRV601