PCF2119RUSLASH2SLASHF2 datasheet(41/79 Pages) NXP

41 / 79 page

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

41 of 79

NXP Semiconductors

PCF2119x

LCD controllers/drivers

11.2 I2C-bus interface

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are the Serial Data line (SDA) and the Serial Clock Line (SCL). Both lines

must be connected to a positive supply via pull-up resistors. Data transfer may be initiated

only when the bus is not busy.

Each byte of eight bits is followed by an acknowledge bit. A slave receiver which is

addressed must generate an acknowledge after the reception of each byte.

Also a master receiver must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter.

The device that acknowledges must pull-down the SDA line during the acknowledge clock

pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge

related clock pulse (set-up and hold times must be taken into consideration).

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge bit on the last byte that has been clocked out of the slave. In this event the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Fig 26. System conﬁguration

Fig 27. Bit transfer

Fig 28. Deﬁnition of START and STOP conditions

mga807

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

mbc621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

mbc622

SDA

SCL

STOP condition

SDA

SCL

START condition

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