SSM2804CBZ-R7 datasheet(19/36 Pages) AD

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SSM2804

Rev. 0 | Page 19 of 36

I2C SOFTWARE CONTROL INTERFACE

The I2C interface provides access to the user-selectable control

registers and operates with a 2-wire interface.

Each control register consists of 16 bits, MSB first. Bits[B15:B9]

are the register map address, and Bits[B8:B0] are the register data

for the associated register map.

SDA generates the serial control data-word, and SCL

clocks the serial data. The I2C bus address (Bits[A7:A1]) is

0x3B (01110110 for write and 01110111 for read). Bit A0 is

the designated read/write bit.

1TO 7

SDA

SCL

START

ADDR

R/W

ACK

SUBADDRESS

ACK

STOP

DATA

Figure 37. 2-Wire I2C Generalized Clocking Diagram

WRITE

SEQUENCE

READ

SEQUENCE

SA1

A(S)

B15

...

A(S)

...

A(M)

...

DEVICE

ADDRESS

DEVICE

ADDRESS

SA1

A(S)

B15

...

DEVICE

ADDRESS

DATA

(SLAVE DRIVE)

DATA

S/P = START/STOP BIT.

A0 = I2C R/W BIT.

A(S) = ACKNOWLEDGE BY SLAVE.

A(M) = ACKNOWLEDGE BY MASTER.

A(M) = ACKNOWLEDGE BY MASTER (INVERSION).

Figure 38. I2C Write and Read Sequences

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