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PCMB065T-R68MS Arkusz danych(PDF) 25 Page - International Rectifier |
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PCMB065T-R68MS Arkusz danych(HTML) 25 Page - International Rectifier |
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25 / 46 page ![]() - 25 - JANURARY 18, 2013 | DATA SHEET | Rev 3.5 25 IR3898 6A Highly Integrated SupIRBuck TM Single-Input Voltage, Synchronous Buck Regulator PD-97662 0.3V 0 0 0 Vp Vsns 0.4V PGood 0.9*Vp 1.2*Vp 1.28ms Figure 16: Vp Tracking (Vref =0V) Internal SS 0 0 0 0 Vref PGood Vsns (0.7V<Vp<3.3V) 0.5V 1.2*Vref 0.9*Vref 0 Vp 0.5V 1.28ms Figure 17: Vp Sequence and Vref Margin OVER-VOLTAGE PROTECTION (OVP) OVP is achieved by comparing Vsns voltage to an OVP threshold voltage. In non-tracking mode, OVP threshold voltage is 1.2×Vref; in tracking mode, it is set at 1.2×Vp. When Vsns exceeds the OVP threshold, an over voltage trip signal asserts after 2us (typ.) delay. Then the control FET is latched off immediately, PGood flags low. The sync FET remains on to discharge the output capacitor. When the Vsns voltage drops below the threshold, the sync FET turns off to prevent the complete depletion of the output capacitor. The control FET remains latched off until user cycle either Vcc or Enable. OVP comparator becomes active only when the device is enabled. Furthermore, for OVP to be active Vref has to exceed 0.2V in non-tracking mode, or Vp has to exceed the threshold in tracking-mode, as illustrated in Fig 18a and Fig 18b. If either of the above conditions is not satisfied, OVP is disabled. Vsns voltage is set by the voltage divider connected to the output and it can be programmed externally. Figure 18c shows the timing diagram for OVP in non-tracking mode. 1.2V En 1.0V Vref 0.2V OVP active region Figure 18a: Activation of OVP in non-tracking mode 1.2V En 1.0V Vp 0.4V OVP active region 0.3V Figure 18b: Activation of OVP in tracking mode HDrv 0 0 0 LDrv Vsns 1.2*Vref 0 PGood 1.15*Vref Figure 18c: Timing Diagram for OVP in non-tracking mode |
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