PCMB065T-R68MS datasheet(27/46 Pages) IRF

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JANURARY 18, 2013 | DATA SHEET | Rev 3.5

IR3898

6A Highly Integrated SupIRBuck

Single-Input Voltage, Synchronous Buck Regulator

PD-97662

MAXIMUM DUTY RATIO

A certain off-time is specified for IR3898. This provides

an upper limit on the operating duty ratio at any given

switching frequency. The off-time remains at a relatively

fixed ratio to switching period in low and mid frequency

range, while in high frequency range this ratio increases,

thus the lower the maximum duty ratio at which IR3898

can operate. Figure 21 shows a plot of the maximum

duty ratio vs. the switching frequency with built in input

voltage feed forward mechanism.

Figure 21: Maximum duty cycle vs. switching frequency.

DESIGN EXAMPLE

The following example is a typical application for IR3898. The

application circuit is shown in Fig.28.

=12 V (

10%)

=1 2 V

= 6 A

Ripple Voltage= 1% *

5% *

50%

=600 kHz

ΔV

load transient



( for

)

Enabling the IR3898

As explained earlier, the precise threshold of the Enable lends

itself well to implementation of a UVLO for the Bus Voltage as

shown in Fig. 22.

IR3898

Enable

Vin

Figure 22: Using Enable pin for UVLO implementation

For a typical Enable threshold of VEN = 1.2 V

(min)

1.2

(7)







min

(8)

in(

)







For Vin (min)=9.2V, R1=49.9K and R2=7.5K ohm is a good choice.

Programming the frequency

For Fs = 600 kHz, select Rt = 39.2 KΩ, using Table 1.

Output Voltage Programming

Output voltage is programmed by reference voltage and

external voltage divider. The Fb pin is the inverting input of

the error amplifier, which is internally referenced to 0.5V.

The divider ratio is set to provide 0.5V at the Fb pin when the

output is at its desired value. The output voltage is defined by

using the following equation:

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