TMS320VC33 datasheet(7/58 Pages) TI

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TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251--1443

Terminal Functions (Continued)

TERMINAL

TYPE†

DESCRIPTION

CONDITIONS

WHEN

NAME

QTY

TYPE†

DESCRIPTION

WHEN

SIGNAL IS Z TYPE‡

TIMER SIGNALS

TCLK0

I/O/Z

Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As

an output, TCLK0 outputs pulses generated by timer 0.

TCLK1

I/O/Z

Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As

an output, TCLK1 outputs pulses generated by timer 1.

SUPPLY AND OSCILLATOR SIGNALS

O/Z

External H1 clock

O/Z

External H3 clock

CVDD

+VDD. Dedicated 1.8-V power supply for the core CPU. All must be connected to

a common supply plane.§

DVDD

+VDD. Dedicated 3.3-V power supply for the I/O pins. All must be connected to a

common supply plane.§

VSS

Ground. All grounds must be connected to a common ground plane.

PLLVDD

Internally isolated PLL supply. Connect to CVDD (1.8 V)

PLLVSS

Internally isolated PLL ground. Connect to VSS

EXTCLK

External clock. Logic level compatible clock input. If the XIN/XOUT oscillator is

used, tie this pin to ground.

XOUT

Clock out. Output from the internal-crystal oscillator. If a crystal is not used, XOUT

should be left unconnected.

XIN

Clock in. Internal-oscillator input from a crystal. If EXTCLK is used, tie this pin to

ground.

CLKMD0,

CLKMD1

Clock mode select pins

RSV0 -- RSV1

Reserved. Use individual pullups to DVDD.

JTAG EMULATION

EMU1--EMU0

I/O

Emulation pins 0 and 1, use individual pullups to DVDD

TDI

Test data input

TDO

Test data output

TCK

Test clock

TMS

Test mode select

TRST

Test reset

† I = input, O = output, Z = high-impedance state

‡ S=SHZ active, H = HOLD active, R = RESET active

§ Recommended decoupling. Four 0.1 μFfor CVDD and eight 0.1 μFfor DVDD.

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