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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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TMS320VC33 Arkusz danych(PDF) 28 Page - Texas Instruments |
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TMS320VC33 Arkusz danych(HTML) 28 Page - Texas Instruments |
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28 / 58 page  TMS320VC33 DIGITAL SIGNAL PROCESSOR SPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 phase-locked loop (PLL) circuit timing switching characteristics over recommended operating conditions for phase-locked loop using EXTCLK or on-chip crystal oscillator† PARAMETER MIN MAX UNIT Fpllin Frequency range, PLL input 5 15 MHz Fpllout Frequency range, PLL output 25 75 MHz Ipll PLL current, CVDD supply 2 mA Ppll PLL power, CVDD supply 5 mW PLLdc PLL output duty cycle at H1 45 55 % PLLJ PLL output jitter, Fpllout =25MHz 400 ps PLLLOCK PLL lock time in input cycles 1000 cycles † Duty cycle is defined as 100*t1/(t1+t2)% To ensure clean internal clock references, the minimal low and high pulse durations must be maintained. At high frequencies, this may require a fast rise and fall time as well as a tightly controlled duty cycle. At lower frequencies, these requirements are less restrictive when in x1 and x0.5 modes. The PLL, however, must have an input duty cycle of between 40% and 60% for proper operation. |
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