TMS320VC33 datasheet(11/58 Pages) TI

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TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251--1443

memory map (continued)

FSX/DX/CLKX Serial Port Control

FSR/DR/CLKR Serial Port Control

Serial R/X Timer Control

Serial R/X Timer Counter

Serial R/X Timer Period Register

Data-Transmit

Data-Receive

Primary-Bus Control

DMA Global Control

DMA Source Address

DMA Destination Address

DMA Transfer Counter

Timer 0 Global Control

Timer 0 Counter

Timer 0 Period Register

Timer 1 Global Control

Timer 1 Counter

Timer 1 Period Register

Serial Global Control

808000h

808004h

808006h

808008h

808020h

808024h

808028h

808030h

808034h

808038h

808040h

808042h

808043h

808044h

808045h

808046h

808048h

80804Ch

808064h

NOTE A: Shading denotes reserved address locations.

Figure 3. Peripheral Bus Memory-Mapped Registers

clock generator

The clock generator provides clocks to the VC33 device, and consists of an internal oscillator and a

phase-locked loop circuit. The clock generator requires a reference clock input, which can be provided by using

a crystal resonator with the internal oscillator, or from an external clock source. The PLL circuit generates the

device clock by multiplying the reference clock frequency by a x5 scale factor, allowing use of a clock source

with a lower frequency than that of the CPU. The PLL is an adaptive circuit that, once synchronized, locks onto

and tracks an input clock signal.

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