| Zakładka z wyszukiwarką danych komponentów |
|
MCP4441 Arkusz danych(PDF) 16 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
MCP4441 Arkusz danych(HTML) 16 Page - Microchip Technology |
|
16 / 100 page ![]() MCP444X/446X DS22265A-page 16 © 2010 Microchip Technology Inc. 107 TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2 400 kHz mode 100 — ns 1.7 MHz mode 10 — ns 3.4 MHz mode 10 — ns 109 TAA Output valid from clock 100 kHz mode — 3450 ns Note 1 400 kHz mode — 900 ns 1.7 MHz mode — 150 ns Cb = 100 pF, Note 1 , Note 7 — 310 ns Cb = 400 pF, Note 1 , Note 5 3.4 MHz mode — 150 ns Cb = 100 pF, Note 1 110 TBUF Bus free time 100 kHz mode 4700 — ns Time the bus must be free before a new transmission can start 400 kHz mode 1300 — ns 1.7 MHz mode N.A. — ns 3.4 MHz mode N.A. — ns TSP Input filter spike suppression (SDA and SCL) 100 kHz mode — 50 ns Philips Spec states N.A. 400 kHz mode — 50 ns 1.7 MHz mode — 10 ns Spike suppression 3.4 MHz mode — 10 ns Spike suppression TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40 °C ≤ TA ≤ +125°C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Param. No. Sym Characteristic Min Max Units Conditions Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. 3: The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: Use Cb in pF for the calculations. 5: Not Tested. 6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. 7: Ensured by the TAA 3.4 MHz specification test. |
|
Link URL |
| Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Link do karty katalogowej | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |