MPC8548ECPXATHC datasheet(71/151 Pages) FREESCALE

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

to AC-coupling. Its value could be ranged from 140

to 240 depending on the clock driver vendor’s

requirement. R2 is used together with the SerDes reference clock receiver’s 50-

 termination resistor to

attenuate the LVPECL output’s differential peak level such that it meets the SerDes reference clock’s

differential input amplitude requirement (between 200 and 800 mV differential peak). For example, if the

LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock input amplitude is

selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25

Consult a clock driver chip

manufacturer to verify whether this connection scheme is compatible with a particular clock driver chip.

Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)

Figure 46 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.

It assumes the DC levels of the clock driver are compatible with the SerDes reference clock input’s DC

requirement.

Figure 46. Single-Ended Connection (Reference Only)

SD_REF_CLK

Clock Driver

100

Differential PWB Trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVPECL CLK Driver Chip

MPC8548E

10 nF

CLK_Out

Clock Driver



SD_REF_CLK

100

Differential PWB Trace

Clock Driver

CLK_Out

Single-Ended CLK

Driver Chip

MPC8548E



Total 50

Assume clock driver’s

output impedance is about 16





SerDes Refer.

CLK Receiver



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