MPC8548ECPXATHC datasheet(17/151 Pages) FREESCALE

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

Freescale Semiconductor

Input Clocks

4.3

eTSEC Gigabit Reference Clock Timing

The following table provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing

specifications for the device.

4.4

PCI/PCI-X Reference Clock Timing

When the PCI/PCI-X controller is configured for asynchronous operation, the reference clock for the

PCI/PCI-x controller is not the SYSCLK input, but instead the PCIn_CLK. The following table provides

the PCI/PCI-X reference clock AC timing specifications for the device.

Table 6. EC_GTX_CLK125 AC Timing Specifications

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Notes

EC_GTX_CLK125 frequency

fG125

—125

—

MHz

—

EC_GTX_CLK125 cycle time

tG125

—8—

EC_GTX_CLK125 rise and fall time

L/TVDD = 2.5 V

L/TVDD = 3.3 V

tG125R, tG125F

——

0.75

1.0

EC_GTX_CLK125 duty cycle

GMII, TBI

1000Base-T for RGMII, RTBI

tG125H/tG125

—

%2, 3

Notes:

1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for L/TVDD = 2.5 V, and from 0.6 and 2.7 V for

L/TVDD = 3.3 V.

2. Timing is guaranteed by design and characterization.

3. EC_GTX_CLK125 is used to generate the GTX clock TSECn_GTX_CLK for the eTSEC transmitter with 2% degradation.

EC_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated

by the TSECn_ GTX_CLK. See Section 8.2.6, “RGMII and RTBI AC Timing Specifications,” for duty cycle for 10Base-T and

100Base-T reference clock.

Table 7. PCIn_CLK AC Timing Specifications

At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Notes

PCIn_CLK frequency

fPCICLK

—

133

MHz

—

PCIn_CLK cycle time

tPCICLK

7.5

—

PCIn_CLK rise and fall time

tPCIKH, tPCIKL

0.6

1.0

2.1

1, 2

PCIn_CLK duty cycle

tPCIKHKL/tPCICLK

—

Notes:

1. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.

2. Timing is guaranteed by design and characterization.

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