MPC8548ECPXATHC datasheet(89/151 Pages) FREESCALE

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

Freescale Semiconductor

Serial RapidIO

18.8

Receiver Eye Diagrams

For each baud rate at which an LP-serial receiver is specified to operate, the receiver shall meet the

corresponding bit error rate specification (Table 66, Table 67, and Table 68) when the eye pattern of the

receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the receiver

input compliance mask shown in Figure 54 with the parameters specified in Table 69. The eye pattern of

the receiver test signal is measured at the input pins of the receiving device with the device replaced with

a 100-

 ± 5% differential resistive load.

Figure 54. Receiver Input Compliance Mask

18.9

Measurement and Test Requirements

Since the LP-serial electrical specification are guided by the XAUI electrical interface specified in

Clause 47 of IEEE Std. 802.3ae-2002, the measurement and test requirements defined here are similarly

guided by Clause 47. Additionally, the CJPAT test pattern defined in Annex 48A of IEEE Std.

Table 69. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter

Receiver Type

VDIFFmin

(mV)

VDIFFmax

(mV)

A (UI)

B (UI)

1.25 GBaud

100

800

0.275

0.400

2.5 GBaud

100

800

0.275

0.400

3.125 GBaud

100

800

0.275

0.400

VDIFF max

–VDIFF max

VDIFF min

–VDIFF min

Time (UI)

1-B

1-A

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