MPC8548ECPXATHC datasheet(12/151 Pages) FREESCALE

12 / 151 page

MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

Freescale Semiconductor

Electrical Characteristics

The following figure shows the undershoot and overshoot voltages at the interfaces of this device.

Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD/BVDD/TVDD

The core voltage must always be provided at nominal 1.1 V. Voltage to the processor interface I/Os are

provided through separate sets of supply pins and must be provided at the voltages shown in Table 2. The

input voltage threshold scales with respect to the associated I/O supply voltage. OVDD and LVDD based

receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR

SDRAM interface uses a single-ended differential receiver referenced the externally supplied MVREF

signal (nominally set to GVDD/2) as is appropriate for the SSTL2 electrical signaling standard.

Junction temperature range

0 to 105

C—

Notes:

1. This voltage is the input to the filter discussed in Section 22.2, “PLL Power Supply Filtering,” and not necessarily the voltage

at the AVDD pin, which may be reduced from VDD by the filter.

2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

4. Caution: L/TVIN must not exceed L/TVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

Table 2. Recommended Operating Conditions (continued)

Characteristic

Symbol

Recommended

Value

Unit

Notes

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

B/G/L/O/TVDD + 20%

B/G/L/O/TVDD

B/G/L/O/TVDD + 5%

of tCLOCK

1. tCLOCK refers to the clock period associated with the respective interface:

VIH

VIL

Notes:

2. Note that with the PCI overshoot allowed (as specified above), the device

does not fully comply with the maximum AC ratings and device protection

guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3).

For I2C and JTAG, tCLOCK references SYSCLK.

For DDR, tCLOCK references MCLK.

For eTSEC, tCLOCK references EC_GTX_CLK125.

For LBIU, tCLOCK references LCLK.

For PCI, tCLOCK references PCIn_CLK or SYSCLK.

For SerDes, tCLOCK references SD_REF_CLK.

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