AM79C970A datasheet(26/219 Pages) AMD

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P R E L I M I N A R Y

Am79C970A

Expansion ROM Interface

ERA[7:0]

Expansion ROM Address

Output

These pins provide the address to the Expansion ROM.

When

EROE is asserted and ERACLK is driven HIGH,

ERA[7:0] contain the upper 8 bits of the Expansion ROM

address. They must be latched externally. When

EROE

is asserted and ERACLK is low, ERA[7:0] contain the

lower 8 bits of the Expansion ROM address.

All ERA outputs are forced to a constant level to con-

serve power while no access to the Expansion ROM

is performed.

ERACLK

Expansion ROM Address Clock

Output

When

EROE is asserted and ERACLK is driven HIGH,

ERA[7:0] contain the upper 8 bits of the Expansion

ROM address. ERACLK is used to latch the address

bits externally. Both ’373 (transparent latch) and ’374

(D flip-flop) types of address latch are supported.

ERD[7:0]

Expansion ROM Data

Input

Data from the Expansion ROM is transferred on

ERD[7:0]. When

EROE is high, the ERD[7:0] inputs are

internally disabled and can be left floating.

Note that the ERD[7:0] pins are multiplexed with the

GPSI interface.

EROE

Expansion ROM Output Enable

Output

This signal is asserted when the Expansion ROM

is read.

Attachment Unit Interface

Collision In

Input

± is a differential input pair signaling the PCnet-PCI II

controller that a collision has been detected on the net-

work media, indicated by the CI

± inputs being driven

with a 10 MHz pattern of sufficient amplitude and pulse

width to meet ISO 8802-3 (IEEE/ANSI 802.3) stan-

dards. Operates at pseudo ECL levels.

Data In

Input

± is a differential input pair to the PCnet-PCI II control-

ler carrying Manchester encoded data from the network.

Operates at pseudo ECL levels.

Data Out

Output

± is a differential output pair from the PCnet-PCI II

controller for transmitting Manchester encoded data to

the network. Operates at pseudo ECL levels.

DXCVR

Disable Transceiver

Output

The DXCVR signal is provided to power down an exter-

nal transceiver or DC-to-DC converter in designs that

provide more than one network connection.

The polarity of the asserted state of the DXCVR output is

controlled by DXCVRPOL (BCR2, bit 4). By default, the

DXCVR output is high when asserted. When the

10BASE-T interface is the active network port, the

DXCVR output is always deasserted. When the AUI or

GPSI interface is the active network port, the assertion

of the DXCVR output is controlled by the setting of

DXCVRCTL (BCR2, bit 5).

Note that the DXCVR pin is multiplexed with the

NOUT pin.

Twisted Pair Interface

LNKST

Link Status

Output

This output is designed to directly drive an LED. By de-

fault,

LNKST indicates an active link connection on the

10BASE-T interface. This pin can also be programmed

to indicate other network status (see BCR4). The

LNKST pin polarity is programmable, but by default, it is

active LOW.

Note that the

LNKST pin is multiplexed with the

EEDI pin.

RXD

10BASE-T Receive Data

Input

10BASE-T port differential receivers.

TXD

10BASE-T Transmit Data

Output

10BASE-T port differential drivers.

TXP

10BASE-T Pre-Distortion Control

Output

These outputs provide transmit pre-distortion control in

conjunction with the 10BASE-T port differential drivers.

General Purpose Serial Interface

CLSN

Collision

Input

CLSN is an input, indicating that a collision has occurred

on the network.

Note that the CLSN pin is multiplexed with the ERD3 pin.

RXCLK

Receive Clock

Input

RXCLK is an input. Rising edges of the RXCLK signal

are used to sample the data on the RXDAT input when-

ever the RXEN input is HIGH.

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