AM79C970A datasheet(81/219 Pages) AMD

81 / 219 page

P R E L I M I N A R Y

AMD

Am79C970A

machine is active as is the collision detection logic. The

programming of MENDECL has no effect in this mode.

Miscellaneous Loopback Features

All transmit and receive function programming, such as

automatic transmit padding and receive pad stripping,

operates identically in loopback as in normal operation.

Loopback mode can be performed with any frame size.

Runt Packet Accept is internally enabled (RPA bit in

CSR124 is not affected) when any loopback mode is in-

voked. This is to be backwards compatible to the

C-LANCE (Am79C90) software.

Since the PCnet-PCI II controller has two FCS genera-

tors there are no more restrictions on FCS generation or

checking or on testing multicast address detection as

they exist in the half-duplex PCnet family devices and in

the C-LANCE and ILACC. On receive the PCnet-PCI II

controller now provides true FCS status. The descriptor

for a frame with an FCS error will have the FCS bit

(RMD1, bit 27) set to ONE. The FCS generator on the

transmit side can still be disabled by setting DXMTFCS

(CSR15, bit 3) to ONE.

In internal loopback operation the PCnet-PCI II control-

ler provides a special mode to test the collision logic.

When FCOLL (CSR15, bit 4) is set to ONE, a collision is

forced during every transmission attempt. This will re-

sult in a Retry error.

Magic Packet Mode

Magic Packet mode is enabled by performing three

steps. First, the PCnet-PCI II controller must be put into

suspend mode (see description of CSR5, bit 0), allowing

any current network activity to finish. Next, MPMODE

(CSR5, bit 1) must be set to ONE if it has not been set

already. Finally, either

SLEEP must be asserted (hard-

ware control) or MPEN (CSR5, bit 2) must be set to ONE

(software control).

In Magic Packet mode, the PCnet-PCI II controller re-

mains fully powered-up (all VDD and VDDB pins must re-

main at their supply levels). The device will not generate

any bus master transfers. No transmit operations will be

initiated on the network. The device will continue to re-

ceive frames from the network, but all frames will be

automatically flushed from the receive FIFO. Slave ac-

cesses to the PCnet-PCI II controller are still possible.

Magic Packet mode can be disabled at any time by

deasserting

SLEEP or clearing MPEN.

A Magic Packet frame is a frame that is addressed to the

PCnet-PCI II controller and contains a data sequence in

its data field made up of sixteen consecutive physical

addresses (PADR[47:0]). The PCnet-PCI II controller

will search incoming frames until it finds a Magic Packet

frame. The device starts scanning for the sequence af-

ter processing the Length field of the frame. The data se-

quence can begin anywhere in the data field of the

frame, but must be detected before the PCnet-PCI II

controller reaches the frame’s FCS field. The PCnet-

PCI II controller is designed such that it does not need

the synchronization sequence (6 bytes of all ONEs

(“FFFFFFFFFFFFh”) at the beginning of the data field),

to correctly recognize the proper data sequence. How-

ever, any deviation of the incoming frame’s Magic Pack-

et data sequence from the required physical address

sequence, even by a single bit, will prevent the detection

of that frame as a Magic Packet frame.

The PCnet-PCI II controller supports two different

modes of address detection for a Magic Packet frame. If

MPPLBA (CSR5, bit 5) is at its default value of ZERO,

the PCnet-PCI II controller will only detect a Magic

Packet frame if the destination address of the frame

matches the content of the physical address register

(PADR). If MPPLBA is set to ONE, the destination ad-

dress of the Magic Packet frame can be unicast, multi-

cast, or broadcast. Note that the setting of MPPLBA

only effects the address detection of the Magic Packet

frame. The Magic Packet data sequence must be made

sixteen

consecutive

physical

addresses

(PADR[47:0]), even if the packet contains a valid desti-

nation address that is not the physical address.

When the PCnet-PCI II controller detects a Magic Pack-

et frame, it sets MPINT (CSR5, bit 4) to ONE. If INEA

(CSR0, bit 6) and MPINTE (CSR5, bit 3) are set to ONE,

INTA will be asserted. The interrupt signal can be used

wake up the system. As an alternative, one of the four

LED pins can be programmed to indicated that a Magic

Packet frame has been received. MPSE (BCR4–7, bit 9)

must be set to ONE to enable that function. Note that the

polarity of the LED pin can be programmed to be active

High by setting LEDPOL (BCR4–7, bit 14) to ONE.

Once a Magic Packet frame is detected, the PCnet-PCI

II controller will discard the frame internally, but will not

resume normal transmit and receive operations until

SLEEP is deasserted or MPEN is cleared, disabling

Magic Packet mode. Once either of these events has

occurred indicating that the system has detected the as-

sertion of

INTA or an LED pin and is now “awake”, the

controller will continue polling the receive and transmit

descriptor rings where it left off. Reinitialization should

not be performed.

If Magic Packet mode is disabled by the deassertion of

SLEEP, then in order to immediately reenable Magic

Packet mode, the

SLEEP pin must remain deasserted

for at least 200 ns before it is reasserted. If Magic Packet

mode is disabled by clearing MPEN, then it may be im-

mediately reenabled by setting MPEN back to ONE.

The bus interface clock (CLK) must continue running if

INTA is used to indicate the detection of a magic packet.

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