AM85C30 datasheet(49/194 Pages) AMD

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I/O Programming Functional Description

AMD

3–18

In this mode the

W/REQ pin carries the DMA Request signal, which is active Low. When

this mode is selected, but not yet enabled, the

W/REQ pin is driven High. When the en-

able bit is set,

W/REQ will go Low if WR8 is empty at the time or will remain High until

WR8 becomes empty. Note that the

W/REQ pin will follow the state of WR8 even though

the transmitter is disabled. Thus, if bit D7 of WR1 is set to ‘1’ (i.e.,

W/REQ pin is enabled)

before the transmitter is enabled, the DMA may write data to the SCC prematurely. This

will not cause a problem in Asynchronous mode but may cause problems in SDLC and

Synchronous modes, because on enabling the transmitter the SCC will send data in pref-

erence to flags or sync characters. It also may complicate the CRC initialization, which

cannot be done until after the transmitter is enabled.

With only one exception, the

W/REQ pin directly follows the state of WR8 in this mode.

W/REQ goes Low when WR8 goes empty and remains Low until the WR8 is filled. The

SCC generates only one falling edge on the

W/REQ pin per character requested. The

timing for this is shown in Figure 3–8.

The one exception occurs at the end of CRC transmission when the SCC is programmed

in either SDLC or Synchronous Modes. At the end of CRC transmission, when the closing

flag or sync character is loaded into the Transmit Shift Register, the

W/REQ pin is pulsed

High for one PCLK cycle. The DMA may use this falling edge on

W/REQ to write the first

character of the next frame or block to the SCC.

W/REQ will go High in response to the

falling edge of

WR, but only when the appropriate WR8 in the SCC is accessed. This is

shown in Figure 3–9.

3.9.3.2

DMA Request on Transmit (Using DTR/REQ)

A second Request on Transmit function is available on the

DTR/REQ pin. This mode is

selected by programming WR14 as shown below.

D6 D5

D4 D3

D2 D1

WR14—DMA Request on Transmit Using DTR/REQ

When this bit is set to ‘1’, the

DTR/REQ pin will go Low if WR8 is empty at the time, or will

go High until WR8 becomes empty. While bit D2 of WR14 is set to ‘0’, the

DTR/REQ pin

is used as a general-purpose output pin and follows the inverted state of bit D7 in WR5.

This pin will be High after a channel or hardware reset and in the DTR mode.

In the DMA Request mode,

DTR/REQ will follow the empty/non-empty state of WR8 even

though the transmitter is disabled. Thus, if the DMA Request function is enabled before

the transmitter is enabled, the DMA may write data to the SCC prematurely. This will not

cause a problem in Asynchronous mode but may cause problems in SDLC and Synchro-

nous modes because the SCC will send data in preference to flags or sync characters. It

also may complicate the CRC initialization, which cannot be done until after the transmit-

ter is enabled and idling. With only one exception, the

DTR/REQ pin directly follows the

state of WR8 in SDLC and Synchronous modes.

DTR/REQ goes Low when WR8 be-

comes empty and remains Low until WR8 is filled. The SCC generates only one falling

edge on the

DTR/REQ pin per character requested and the timing for this is shown in

Figure 3–8.

The one exception occurs in SDLC and Synchronous modes at the end of CRC transmis-

sion. At the end of CRC transmission, when the closing flag or sync character is loaded

into the Transmit Shift Register,

DTR/REQ is pulsed High for one PCLK cycle. The DMA

may use this falling edge on

DTR/REQ to write the first character of the next frame or

block to the SCC.

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