AM85C30 datasheet(11/194 Pages) AMD

11 / 194 page

1–3

General Information

CHAPTER 1

1.1

INTRODUCTION

The Am85C30 and Am8530H SCCs (Serial Communications Controller) are dual chan-

nel, multiprotocol data communications peripherals designed for use with 8- and 16-bit

microprocessors. The SCC functions as a serial-to-parallel, parallel-to-serial converter/

controller. The SCC can be software configured to satisfy a wide variety of serial commu-

nications applications, including: Bus Architectures (full- and half-duplex), Token Passing

Ring (SDLC Loop mode), and Star configurations (similar to SLAN).

The SCC contains a variety of internal functions including on-chip baud rate generators,

digital phase-lock loops, and crystal oscillators, which dramatically reduce the need for

external logic. In addition, SDLC/HDLC enhancements have been added to the Am85C30

that allow it to be used more effectively in high speed applications.

The SCC handles asynchronous formats, synchronous character-oriented protocols such

as IBM BISYNC, and Synchronous bit-oriented protocols such HDLC and IBM SDLC.

This versatile device supports virtually any serial data transfer application (telecommuni-

cations, cassette, diskette, tape drivers, etc.).

The device can generate and check CRC codes in any Synchronous mode. The SCC

also has facilities for Modem controls in both channels. In applications where these con-

trols are not needed, the Modem controls can be used for general purpose I/O.

With access to the Write registers and Read registers in each channel, the user can con-

figure the SCC so that it can handle all asynchronous formats regardless of data size,

number of stop bits, or parity requirements. The SCC also accommodates all synchro-

nous formats including character, byte, and bit-oriented protocols.

Within each operating mode, the SCC also allows for protocol variations by handling odd

or even parity bits, character insertion or deletion, CRC generation and checking, break/

abort generation and detection, and many other protocol-dependent features.

Unless otherwise stated, the functional description in this Technical Manual applies to

both the NMOS Am8530H and CMOS Am85C30. When the enhancements in the

Am85C30 are disabled, it is completely downward compatible with the Am8530H.

1.2

CAPABILITIES

s Two independent full-duplex channels

s Synchronous data rates:

– Up to 1/4 of the PCLK (i.e., 4 Mbit/sec. maximum data rate with 16 MHz PCLK

Am85C30)

– Up to 1Mbit/second with a 16 MHz clock rate (FM encoding using DPLL in

Am85C30)

– Up to 500 Kbit/second with 16 MHz clock rate (NRZI encoding using DPLL in

Am85C30)

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