AM85C30 datasheet(80/194 Pages) AMD

80 / 194 page

Data Communication Modes Functional Description

AMD

4–28

(so the Reset Tx CRC Generator command is also not necessary), and the Tx Underrun/

EOM latch will be reset automatically on every new frame sent. This ensures that an

opening flag and proper CRC generation and transmission will always be sent without

processor intervention under varying bus latency conditions.

4.8.4

Abort Generation

The premature termination of a frame is called an “abort”. A properly transmitted SDLC

frame will be terminated by appending the CRC characters and a closing flag, but the

SCC may be programmed to terminate the frame by sending an abort and a flag instead.

This option allows the SCC to abort the transmission of a frame in progress and at the

same time signify to the receiver that another frame will follow.

This is controlled by the ABORT/FLAG on Underrun bit in WR10 (D2). When this bit is

set to ‘1’, and an underrun occurs, the transmitter will transmit an abort immediately fol-

lowed by a flag instead of the normal CRC. If this bit is set to ‘0’, the frame will be termi-

nated normally.

The processor is also able to send an abort by issuing the Send Abort command via

WR0. This command, when issued, will send eight consecutive ‘1’s. After this pattern is

transmitted, the transmitter will idle as programmed via bit D3 of WR10. Since up to five

consecutive ‘1’s may have been sent prior to the command being issued, a Send Abort

may cause a sequence of from eight to thirteen ‘1’s to be transmitted. The Send Abort

command also empties the transmit buffer register and sets the Tx Underrun/EOM bit in

RR0.

4.8.5

Auto Transmit CRC Generator Preset

The NMOS SCC does not automatically preset the CRC generator prior to frame trans-

mission. This must be done in software, usually during the initialization routine. This is

accomplished by issuing the Reset Tx CRC Generator Command via WR0. For proper

results, this command must be issued while the transmitter is enabled and idling and be-

fore any data are written to the Transmit Buffer.

In addition, if CRC is to be used, the transmit CRC generator must be enabled by setting

bit D0 of WR5 to ‘1’. CRC is normally calculated on all characters between opening and

closing flags, so this bit should be set to ‘1’ at initialization and never changed. Note that

a Channel Reset will not initialize the CRC generator so a Reset Tx CRC Generator com-

mand must be issued some time after a Channel Reset is executed.

On the CMOS SCC, setting bit D0 of WR15 ‘1’ will cause the transmit CRC generator to

be preset automatically every time an opening flag is sent, so the Reset Tx CRC Genera-

tor command is not necessary.

4.8.6

CRC Transmission

The transmission of the CRC check characters is controlled by the Transmit CRC Enable

bit in WR5 (D0) and the Tx Underrun/EOM bit in RR0 (D6). However, if the Transmit CRC

Enable bit is set to ‘0’ when a transmit underrun (i.e., both the Transmit Buffer and Trans-

mit Shift Register go empty) occurs, the CRC check characters will not be sent regardless

of the state of the Tx Underrun/EOM bit.

If the Transmit CRC Enable bit is set to ‘1’ when an underrun occurs, then the state of the

Tx Underrun/EOM bit and the Abort/Flag on Underrun bit in WR10 (D2) determine the

action taken by the transmitter. The Abort/Flag on Underrun bit may be set or reset by the

processor, whereas, the Tx Underrun/EOM bit is set by the transmitter and can be reset

only by the processor via the Reset Tx Underrun/EOM command in WR0.

If the Tx Underrun/EOM bit is set to ‘1’ when an underrun occurs, the transmitter will

close the frame by sending a flag; however, if this bit is set to ‘0’, the frame data will be

appended with either the accumulated CRC characters followed by a flag or an abort pat-

tern followed by a flag, depending on the state of the Abort/Flag on Underrun bit in the

WR10 (D2). In either case, after the closing flag is sent, the Transmitter will idle the trans-

mission line as specified by the Mark/Flag Idle bit D3 in WR10.

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