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L6717

Hybrid CPU support and CPU_TYPE detection

Doc ID 17326 Rev 1

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Hybrid CPU support and CPU_TYPE detection

L6717 is able to detect the type of the CPU-core connected and to configure itself

accordingly. At system Start-up, on the rising-edge of the EN signal, the device monitors the

status of VID1 and configures the PVI mode (VID1 = 1) or SVI mode (VID1 = 0).

When in PVI mode, L6717 uses the information available on the VID[0: 5] bus to address the

CORE Section output voltage according to Table 6. NB Section is kept in HiZ mode, both

MOSFETs are kept OFF.

When in SVI mode, L6717 ignores the information available on VID0, VID4 and VID5 and

uses VID2 and VID3 as a SVI bus addressing the CORE and NB Sections according to the

SVI protocol.

Caution:

To avoid any risk of errors in CPU type detection (i.e. detecting SVI CPU when PVI CPU is

installed on the socket and vice versa), it is recommended to carefully control the start-up

sequencing of the system hosting L6717 in order to ensure than on the EN rising-edge,

VID1 is in valid and correct state. Typical connections consider VID1 connected to CPU

CORE_TYPE through a resistor to correctly address the CPU detection.

5.1

PVI - parallel interface

PVI is a 6-bit-wide parallel interface used to address the CORE section reference. According

to the selected code, the device sets the CORE section reference and regulates its output

voltage as reported into Table 6.

NB section is always kept in HiZ; no activity is performed on this section and both the high-

side and low-side of this section are kept OFF. Furthermore, PWROK information is ignored

as well since the signal only applies to the SVI protocol.

5.2

PVI start-up

Once the PVI mode has been detected, the device uses the whole code available on the

VID[0:5] lines to define the reference for the CORE section. NB section is kept in HiZ. Soft-

start to the programmed reference is performed regardless of the state of PWROK.

See Section 7.8 for details about soft-start.

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