L6717 datasheet(44/56 Pages) STMICROELECTRONICS

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Output voltage monitoring and protections

L6717

44/56

Doc ID 17326 Rev 1

scale can be implemented. When the voltage present at the ILIM pin crosses

VOC_TOT, the device detects an OC and immediately latches with all the MOSFETs

of all the sections OFF (HiZ).

Typical design considers the intervention of the total current OC before the per-phase OC,

leaving this last one as an extreme-protection in case of hardware failures in the external

components. Typical design flow is the following:

–

Define the maximum total output current (IOC_TOT) according to system

requirements

–

Design per-phase OC and RG resistor in order to have IINFOx = IOC_TH (35 μA)

when IOUT is about 10% higher than the IOC_TOT current. It results:

where N is the number of phases and DCR the DC resistance of the inductors. RG

should be designed in worst-case conditions.

–

Design the total current OC and RILIM in order to have the ILIM pin voltage to

VOC_TOT at the desired maximum current IOC_TOT. It results:

where VOC_TOT is typically 2.5V and IOC_TOT is the total current OC threshold

desired.

–

Adjust the defined values according to bench-test of the application.

–

An additional capacitor in parallel to RILIM can be considered to add a delay in the

protection intervention.

Note:

What previously listed is the typical design flow. Custom design and specifications may

require different settings and ratios between the per-phase OC threshold and the Total

Current OC threshold. Applications with huge ripple across inductors may be required to set

per-phase OC to values different than 110%: design flow should be modified accordingly.

Note:

DRP_ADJ command from power manager I2C does not alter the current information used

for per-phase OC and total current OC.

1.1 I

OC_TOT

⋅

() DCR

⋅

OCTH

--------------------------------------------------------

ILIM

OC_TOT

⋅

OC_TOT

DCR

⋅

---------------------------------------

LIM

DCR

------------- I

OUT

⋅

⎝⎠

⎛⎞

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