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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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UPD17015GS Arkusz danych(PDF) 49 Page - NEC |
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UPD17015GS Arkusz danych(HTML) 49 Page - NEC |
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49 / 120 page  49 µPD17015 (2) When the BTM0CY flag is detected simultaneously with a CE reset As described in (1), a CE reset occurs at the same time the BTM0CY flag is set (1). Under this condition, if a read instruction is executed for the BTM0CY flag simultaneously with a CE reset, the read instruction takes preference. Therefore, if a BTM0CY flag read instruction occurs simultaneously with the rising edge of the BTM0CY flag set pulse that occurs after the CE pin goes from a low to a high, a CE reset occurs when the BTM0CY flag is set on the next cycle. This operation is illustrated in Fig. 10-7. Fig. 10-7 Operation That Occurs If a CE Reset Occurs Simultaneously with a BTM0CY Flag Read Instruction H L H L 1 0 SKT 1 BTM0CY SKT 1 BTM0CY CE reset H L 1 0 SKT1 BTM0CY CE pin BTM0CY flag set pulse BTM0CY flag BTM0CY flag set pulse BTM0CY flag Instruction 53.3 s If the BTM0CY flag is read during this period, a CE reset is deferred by one cycle. Normally, the program starts at address 000H at this point, but a CE reset does occur because the program to read the BTM0CY flag also happens to run. µ |
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