UPD17015GS datasheet(2/120 Pages) NEC

2 / 120 page

µPD17015

FUNCTION OVERVIEW

Item

Function

Program memory (ROM)

• 3K bytes (1528

× 16 bits)

General-purpose data memory

• 97

× 4 bits

Instruction execution time

• 53.3

µs (when 75 kHz crystal is used)

Stack levels

• 1 level

General-purpose ports

• I/O

: 2 ports

• Input only

: 3 ports

• Output only : 7 ports

BEEP output

1 (3 kHz)

LCD controller/driver

• 9 segments, 4 commons

• 1/4 duty, 1/2 bias, frame frequency 62.5 Hz, driving voltage 3.0 V (TYP.)

Timers

2 channels

Basic timer 0 : 125 ms

Basic timer 1 : 5 ms

Reset

• Power-on reset

• Reset with the CE pin (by switching the CE pin from low to high)

• Power-failure detection function

PLL

Frequency division

• Direct division method

(VCOL pin (MF mode)

8 MHz MAX.)

frequency

method

• Pulse swallow method

(VCOL pin (HF mode)

55MHz MAX.)

synthesizer

(VCOH pin (VHF mode) : 220MHz MAX.)

Reference frequency

1, 3, 5, or 25 kHz, selected by software.

Charge pump

Error-out output: 1

Phase comparator

An unlocked state can be detected by software.

Supply voltage

• 1.8 to 3.6 V (TA = –10 to +50

°C)

• 1.9 to 3.6 V (TA = –20 to +50

°C)

Package

38-pin plastic shrink SOP (0.65-mm pitches, 300 mil)

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